#ifndef __ARCH_SPARC_UTILITY_HH__
#define __ARCH_SPARC_UTILITY_HH__
-#include "arch/sparc/faults.hh"
#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/registers.hh"
#include "arch/sparc/tlb.hh"
-#include "base/misc.hh"
#include "base/bitfield.hh"
+#include "base/misc.hh"
+#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "sim/fault_fwd.hh"
+#include "sim/full_system.hh"
namespace SparcISA
{
- static inline bool
- inUserMode(ThreadContext *tc)
- {
- return !(tc->readMiscRegNoEffect(MISCREG_PSTATE & (1 << 2)) ||
- tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2)));
- }
-
- inline bool isCallerSaveIntegerRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
- inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
- inline bool isCallerSaveFloatRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
- inline bool isCalleeSaveFloatRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
- // Instruction address compression hooks
- inline Addr realPCToFetchPC(const Addr &addr)
- {
- return addr;
- }
-
- inline Addr fetchPCToRealPC(const Addr &addr)
- {
- return addr;
- }
-
- // the size of "fetched" instructions (not necessarily the size
- // of real instructions for PISA)
- inline size_t fetchInstSize()
- {
- return sizeof(MachInst);
- }
-
- /**
- * Function to insure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
- template <class TC>
- void zeroRegisters(TC *tc);
-
- inline void initCPU(ThreadContext *tc, int cpuId)
- {
- static Fault por = new PowerOnReset();
- if (cpuId == 0)
- por->invoke(tc);
-
- }
-
- inline void startupCPU(ThreadContext *tc, int cpuId)
- {
-#if FULL_SYSTEM
- // Other CPUs will get activated by IPIs
- if (cpuId == 0)
- tc->activate(0);
-#else
+inline PCState
+buildRetPC(const PCState &curPC, const PCState &callPC)
+{
+ PCState ret = callPC;
+ ret.uEnd();
+ ret.pc(curPC.npc());
+ return ret;
+}
+
+uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
+
+static inline bool
+inUserMode(ThreadContext *tc)
+{
+ PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
+ HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
+ return !(pstate.priv || hpstate.hpriv);
+}
+
+/**
+ * Function to insure ISA semantics about 0 registers.
+ * @param tc The thread context.
+ */
+template <class TC>
+void zeroRegisters(TC *tc);
+
+void initCPU(ThreadContext *tc, int cpuId);
+
+inline void
+startupCPU(ThreadContext *tc, int cpuId)
+{
+ // Other CPUs will get activated by IPIs
+ if (cpuId == 0 || !FullSystem)
tc->activate(0);
-#endif
- }
+}
+
+void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
+void skipFunction(ThreadContext *tc);
+
+inline void
+advancePC(PCState &pc, const StaticInstPtr inst)
+{
+ inst->advancePC(pc);
+}
+
+inline uint64_t
+getExecutingAsid(ThreadContext *tc)
+{
+ return tc->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
+}
} // namespace SparcISA