arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / vtophys.cc

diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc
index c8f35fe8b9f91ab08ae1699f853ffb30f895188e..88f1c4acebbbe256b8048c0d708486ae25580204 100644 (file)
--- a/src/arch/sparc/vtophys.cc
+++ b/src/arch/sparc/vtophys.cc
@@ -28,15 +28,17 @@
  * Authors: Ali Saidi
  */
 
+#include "arch/sparc/vtophys.hh"
+
 #include <string>
 
 #include "arch/sparc/tlb.hh"
-#include "arch/sparc/vtophys.hh"
 #include "base/chunk_generator.hh"
 #include "base/compiler.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
-#include "mem/vport.hh"
+#include "debug/VtoPhys.hh"
+#include "mem/port_proxy.hh"
 
 using namespace std;
 
@@ -80,9 +82,9 @@ vtophys(ThreadContext *tc, Addr addr)
     int pri_context = bits(tlbdata,47,32);
     // int sec_context = bits(tlbdata,63,48);
 
-    FunctionalPort *mem = tc->getPhysPort();
-    TLB* itb = tc->getITBPtr();
-    TLB* dtb = tc->getDTBPtr();
+    PortProxy &mem = tc->getPhysProxy();
+    TLB* itb = dynamic_cast<TLB *>(tc->getITBPtr());
+    TLB* dtb = dynamic_cast<TLB *>(tc->getDTBPtr());
     TlbEntry* tbe;
     PageTableEntry pte;
     Addr tsbs[4];
@@ -109,9 +111,9 @@ vtophys(ThreadContext *tc, Addr addr)
     dtb->GetTsbPtr(tc, addr, ctx_zero ? 0 : pri_context, tsbs);
     va_tag = bits(addr, 63, 22);
     for (int x = 0; x < 4; x++) {
-        ttetag = betoh(mem->read<uint64_t>(tsbs[x]));
+        ttetag = betoh(mem.read<uint64_t>(tsbs[x]));
         if (ttetag.valid() && ttetag.va() == va_tag) {
-            uint64_t entry = mem->read<uint64_t>(tsbs[x]) + sizeof(uint64_t);
+            uint64_t entry = mem.read<uint64_t>(tsbs[x]) + sizeof(uint64_t);
             // I think it's sun4v at least!
             pte.populate(betoh(entry), PageTableEntry::sun4v);
             DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TTE\n",