X86: Use IsSquashAfter if an instruction could affect fetch translation.

[gem5.git] / src / arch / x86 / SConscript

diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 9cb774647568bfa67cf14fad3bd07d8aaf143c9f..2742c79e85f4f096453d3b8a4210573fff194a77 100644 (file)
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -66,14 +66,14 @@ if env['TARGET_ISA'] == 'x86':
     SimObject('X86NativeTrace.py')
 
     SimObject('X86TLB.py')
-    TraceFlag('Predecoder', "Predecoder debug output")
-    TraceFlag('X86', "Generic X86 ISA debugging")
+    DebugFlag('Predecoder', "Predecoder debug output")
+    DebugFlag('X86', "Generic X86 ISA debugging")
 
     if env['FULL_SYSTEM']:
-        TraceFlag('LocalApic', "Local APIC debugging")
-        TraceFlag('PageTableWalker', \
+        DebugFlag('LocalApic', "Local APIC debugging")
+        DebugFlag('PageTableWalker', \
                   "Page table walker state machine debugging")
-        TraceFlag('Faults', "Trace all faults/exceptions/traps")
+        DebugFlag('Faults', "Trace all faults/exceptions/traps")
 
         SimObject('X86LocalApic.py')
         SimObject('X86System.py')