from m5.params import *
from m5.proxy import *
-from BaseTLB import BaseTLB
-from MemObject import MemObject
+from m5.objects.BaseTLB import BaseTLB
+from m5.objects.ClockedObject import ClockedObject
-class X86PagetableWalker(MemObject):
+class X86PagetableWalker(ClockedObject):
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
- port = Port("Port for the hardware table walker")
+ cxx_header = 'arch/x86/pagetable_walker.hh'
+ port = MasterPort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
+ num_squash_per_cycle = Param.Unsigned(4,
+ "Number of outstanding walks that can be squashed per cycle")
class X86TLB(BaseTLB):
type = 'X86TLB'
cxx_class = 'X86ISA::TLB'
- size = Param.Int(64, "TLB size")
+ cxx_header = 'arch/x86/tlb.hh'
+ size = Param.Unsigned(64, "TLB size")
walker = Param.X86PagetableWalker(\
X86PagetableWalker(), "page table walker")