* Authors: Gabe Black
*/
-#include "arch/x86/decoder.hh"
+#include "arch/x86/generated/decoder.hh"
#include "arch/x86/faults.hh"
+#include "arch/x86/isa_traits.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
#include "cpu/thread_context.hh"
-#if !FULL_SYSTEM
-#include "arch/x86/isa_traits.hh"
-#include "mem/page_table.hh"
-#include "sim/process.hh"
-#else
-#include "arch/x86/tlb.hh"
-#endif
+#include "debug/Faults.hh"
+#include "sim/full_system.hh"
namespace X86ISA
{
-#if FULL_SYSTEM
void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
{
- Addr pc = tc->readPC();
- DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
+ if (!FullSystem) {
+ FaultBase::invoke(tc, inst);
+ return;
+ }
+
+ PCState pcState = tc->pcState();
+ Addr pc = pcState.pc();
+ DPRINTF(Faults, "RIP %#x: vector %d: %s\n",
+ pc, vector, describe());
using namespace X86ISAInst::RomLabels;
HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
MicroPC entry;
panic("Legacy mode interrupts with error codes "
"aren't implementde.\n");
}
- // Software interrupts shouldn't have error codes. If one does,
- // there would need to be microcode to set it up.
+ // Software interrupts shouldn't have error codes. If one
+ // does, there would need to be microcode to set it up.
assert(!isSoft());
tc->setIntReg(INTREG_MICRO(15), errorCode);
}
- tc->setMicroPC(romMicroPC(entry));
- tc->setNextMicroPC(romMicroPC(entry) + 1);
+ pcState.upc(romMicroPC(entry));
+ pcState.nupc(romMicroPC(entry) + 1);
+ tc->pcState(pcState);
}
std::string
void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
{
X86FaultBase::invoke(tc);
- // This is the same as a fault, but it happens -after- the instruction.
- tc->setPC(tc->readNextPC());
- tc->setNextPC(tc->readNextNPC());
- tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
+ if (!FullSystem)
+ return;
+
+ // This is the same as a fault, but it happens -after- the
+ // instruction.
+ PCState pc = tc->pcState();
+ pc.uEnd();
}
void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
panic("Abort exception!");
}
+ void
+ InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
+ {
+ if (FullSystem) {
+ X86Fault::invoke(tc, inst);
+ } else {
+ panic("Unrecognized/invalid instruction executed:\n %s",
+ inst->machInst);
+ }
+ }
+
void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
{
- HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
- X86FaultBase::invoke(tc);
- /*
- * If something bad happens while trying to enter the page fault
- * handler, I'm pretty sure that's a double fault and then all bets are
- * off. That means it should be safe to update this state now.
- */
- if (m5reg.mode == LongMode) {
- tc->setMiscReg(MISCREG_CR2, addr);
+ if (FullSystem) {
+ HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
+ X86FaultBase::invoke(tc);
+ /*
+ * If something bad happens while trying to enter the page fault
+ * handler, I'm pretty sure that's a double fault and then all
+ * bets are off. That means it should be safe to update this
+ * state now.
+ */
+ if (m5reg.mode == LongMode) {
+ tc->setMiscReg(MISCREG_CR2, addr);
+ } else {
+ tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
+ }
} else {
- tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
+ PageFaultErrorCode code = errorCode;
+ const char *modeStr = "";
+ if (code.fetch)
+ modeStr = "execute";
+ else if (code.write)
+ modeStr = "write";
+ else
+ modeStr = "read";
+ panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
}
}
tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
- tc->setPC(0x000000000000fff0ULL +
- tc->readMiscReg(MISCREG_CS_BASE));
- tc->setNextPC(tc->readPC() + sizeof(MachInst));
+ PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE));
+ tc->pcState(pc);
tc->setMiscReg(MISCREG_TSG_BASE, 0);
tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
+ tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
+
+ // Flag all elements on the x87 stack as empty.
+ tc->setMiscReg(MISCREG_FTW, 0xFFFF);
+
// Update the handy M5 Reg.
tc->setMiscReg(MISCREG_M5_REG, 0);
MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
- tc->setMicroPC(romMicroPC(entry));
- tc->setNextMicroPC(romMicroPC(entry) + 1);
+ pc.upc(romMicroPC(entry));
+ pc.nupc(romMicroPC(entry) + 1);
+ tc->pcState(pc);
}
void
// This has the base value pre-added.
tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
- tc->setPC(tc->readMiscReg(MISCREG_CS_BASE));
- tc->setNextPC(tc->readPC() + sizeof(MachInst));
+ tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
}
-
-#else
-
- void
- InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
- {
- panic("Unrecognized/invalid instruction executed:\n %s",
- inst->machInst);
- }
-
- void
- PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
- {
- PageFaultErrorCode code = errorCode;
- const char *modeStr = "";
- if (code.fetch)
- modeStr = "execute";
- else if (code.write)
- modeStr = "write";
- else
- modeStr = "read";
- panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
- }
-
-#endif
} // namespace X86ISA
projects / gem5.git / blobdiff