/*
- * Copyright (c) 2008 The Hewlett-Packard Development Company
- * All rights reserved.
+ * Copyright (c) 2012-2013 ARM Limited
+ * All rights reserved
*
- * Redistribution and use of this software in source and binary forms,
- * with or without modification, are permitted provided that the
- * following conditions are met:
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
*
- * The software must be used only for Non-Commercial Use which means any
- * use which is NOT directed to receiving any direct monetary
- * compensation for, or commercial advantage from such use. Illustrative
- * examples of non-commercial use are academic research, personal study,
- * teaching, education and corporate research & development.
- * Illustrative examples of commercial use are distributing products for
- * commercial advantage and providing services using the software for
- * commercial advantage.
+ * Copyright (c) 2008 The Hewlett-Packard Development Company
+ * All rights reserved.
*
- * If you wish to use this software or functionality therein that may be
- * covered by patents for commercial use, please contact:
- * Director of Intellectual Property Licensing
- * Office of Strategy and Technology
- * Hewlett-Packard Company
- * 1501 Page Mill Road
- * Palo Alto, California 94304
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
*
- * Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer. Redistributions
- * in binary form must reproduce the above copyright notice, this list of
- * conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution. Neither the name of
- * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission. No right of
- * sublicense is granted herewith. Derivatives of the software and
- * output created using the software may be prepared, but only for
- * Non-Commercial Uses. Derivatives of the software may be shared with
- * others provided: (i) the others agree to abide by the list of
- * conditions herein which includes the Non-Commercial Use restrictions;
- * and (ii) such Derivatives of the software include the above copyright
- * notice to acknowledge the contribution from this software where
- * applicable, this list of conditions and the disclaimer below.
+ * this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Authors: Gabe Black
*/
-#include "arch/x86/apicregs.hh"
#include "arch/x86/interrupts.hh"
+
+#include <list>
+#include <memory>
+
+#include "arch/x86/intmessage.hh"
+#include "arch/x86/regs/apic.hh"
#include "cpu/base.hh"
+#include "debug/LocalApic.hh"
+#include "dev/x86/i82094aa.hh"
+#include "dev/x86/pc.hh"
+#include "dev/x86/south_bridge.hh"
+#include "mem/packet_access.hh"
+#include "sim/full_system.hh"
+#include "sim/system.hh"
int
divideFromConf(uint32_t conf)
regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
break;
case 0x100:
- case 0x108:
case 0x110:
- case 0x118:
case 0x120:
- case 0x128:
case 0x130:
- case 0x138:
case 0x140:
- case 0x148:
case 0x150:
- case 0x158:
case 0x160:
- case 0x168:
case 0x170:
- case 0x178:
- regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
+ regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x10);
break;
case 0x180:
- case 0x188:
case 0x190:
- case 0x198:
case 0x1A0:
- case 0x1A8:
case 0x1B0:
- case 0x1B8:
case 0x1C0:
- case 0x1C8:
case 0x1D0:
- case 0x1D8:
case 0x1E0:
- case 0x1E8:
case 0x1F0:
- case 0x1F8:
- regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
+ regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x10);
break;
case 0x200:
- case 0x208:
case 0x210:
- case 0x218:
case 0x220:
- case 0x228:
case 0x230:
- case 0x238:
case 0x240:
- case 0x248:
case 0x250:
- case 0x258:
case 0x260:
- case 0x268:
case 0x270:
- case 0x278:
- regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
+ regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x10);
break;
case 0x280:
regNum = APIC_ERROR_STATUS;
X86ISA::Interrupts::read(PacketPtr pkt)
{
Addr offset = pkt->getAddr() - pioAddr;
- //Make sure we're at least only accessing one register.
+ // Make sure we're at least only accessing one register.
if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
panic("Accessed more than one register at a time in the APIC!\n");
ApicRegIndex reg = decodeAddr(offset);
- uint32_t val = htog(readReg(reg));
+ uint32_t val = htole(readReg(reg));
DPRINTF(LocalApic,
"Reading Local APIC register %d at offset %#x as %#x.\n",
reg, offset, val);
pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
- return latency;
+ pkt->makeAtomicResponse();
+ return pioDelay;
}
Tick
X86ISA::Interrupts::write(PacketPtr pkt)
{
Addr offset = pkt->getAddr() - pioAddr;
- //Make sure we're at least only accessing one register.
+ // Make sure we're at least only accessing one register.
if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
panic("Accessed more than one register at a time in the APIC!\n");
ApicRegIndex reg = decodeAddr(offset);
pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
DPRINTF(LocalApic,
"Writing Local APIC register %d at offset %#x as %#x.\n",
- reg, offset, gtoh(val));
- setReg(reg, gtoh(val));
- return latency;
+ reg, offset, letoh(val));
+ setReg(reg, letoh(val));
+ pkt->makeAtomicResponse();
+ return pioDelay;
+}
+void
+X86ISA::Interrupts::requestInterrupt(uint8_t vector,
+ uint8_t deliveryMode, bool level)
+{
+ /*
+ * Fixed and lowest-priority delivery mode interrupts are handled
+ * using the IRR/ISR registers, checking against the TPR, etc.
+ * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
+ */
+ if (deliveryMode == DeliveryMode::Fixed ||
+ deliveryMode == DeliveryMode::LowestPriority) {
+ DPRINTF(LocalApic, "Interrupt is an %s.\n",
+ DeliveryMode::names[deliveryMode]);
+ // Queue up the interrupt in the IRR.
+ if (vector > IRRV)
+ IRRV = vector;
+ if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
+ setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
+ if (level) {
+ setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
+ } else {
+ clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
+ }
+ }
+ } else if (!DeliveryMode::isReserved(deliveryMode)) {
+ DPRINTF(LocalApic, "Interrupt is an %s.\n",
+ DeliveryMode::names[deliveryMode]);
+ if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
+ pendingUnmaskableInt = pendingSmi = true;
+ smiVector = vector;
+ } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
+ pendingUnmaskableInt = pendingNmi = true;
+ nmiVector = vector;
+ } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
+ pendingExtInt = true;
+ extIntVector = vector;
+ } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
+ pendingUnmaskableInt = pendingInit = true;
+ initVector = vector;
+ } else if (deliveryMode == DeliveryMode::SIPI &&
+ !pendingStartup && !startedUp) {
+ pendingUnmaskableInt = pendingStartup = true;
+ startupVector = vector;
+ }
+ }
+ if (FullSystem)
+ cpu->wakeup(0);
+}
+
+
+void
+X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
+{
+ assert(newCPU);
+ if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
+ panic("Local APICs can't be moved between CPUs"
+ " with different IDs.\n");
+ }
+ cpu = newCPU;
+ initialApicId = cpu->cpuId();
+ regs[APIC_ID] = (initialApicId << 24);
+ pioAddr = x86LocalAPICAddress(initialApicId, 0);
+}
+
+
+void
+X86ISA::Interrupts::init()
+{
+ panic_if(!intMasterPort.isConnected(),
+ "Int port not connected to anything!");
+ panic_if(!pioPort.isConnected(),
+ "Pio port of %s not connected to anything!", name());
+
+ intSlavePort.sendRangeChange();
+ pioPort.sendRangeChange();
}
+
Tick
X86ISA::Interrupts::recvMessage(PacketPtr pkt)
{
- Addr offset = pkt->getAddr() - x86InterruptAddress(0, 0);
- assert(pkt->cmd == MemCmd::MessageReq);
+ Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
+ assert(pkt->cmd == MemCmd::WriteReq);
switch(offset)
{
case 0:
- DPRINTF(LocalApic, "Got Trigger Interrupt message.\n");
+ {
+ TriggerIntMessage message = pkt->getRaw<TriggerIntMessage>();
+ DPRINTF(LocalApic,
+ "Got Trigger Interrupt message with vector %#x.\n",
+ message.vector);
+
+ requestInterrupt(message.vector,
+ message.deliveryMode, message.trigger);
+ }
break;
default:
panic("Local apic got unknown interrupt message at offset %#x.\n",
offset);
break;
}
- delete pkt->req;
+ pkt->makeAtomicResponse();
+ return pioDelay;
+}
+
+
+void
+X86ISA::Interrupts::completeIPI(PacketPtr pkt)
+{
+ if (--pendingIPIs == 0) {
+ InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
+ // Record that the ICR is now idle.
+ low.deliveryStatus = 0;
+ regs[APIC_INTERRUPT_COMMAND_LOW] = low;
+ }
+ DPRINTF(LocalApic, "ICR is now idle.\n");
delete pkt;
- return latency;
+}
+
+
+AddrRangeList
+X86ISA::Interrupts::getAddrRanges() const
+{
+ assert(cpu);
+ AddrRangeList ranges;
+ ranges.push_back(RangeSize(pioAddr, PageBytes));
+ return ranges;
+}
+
+
+AddrRangeList
+X86ISA::Interrupts::getIntAddrRange() const
+{
+ AddrRangeList ranges;
+ ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
+ x86InterruptAddress(initialApicId, 0) +
+ PhysAddrAPICRangeSize));
+ return ranges;
}
case APIC_PROCESSOR_PRIORITY:
panic("Local APIC Processor Priority register unimplemented.\n");
break;
- case APIC_EOI:
- panic("Local APIC EOI register unimplemented.\n");
- break;
case APIC_ERROR_STATUS:
regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
break;
- case APIC_INTERRUPT_COMMAND_LOW:
- panic("Local APIC Interrupt Command low"
- " register unimplemented.\n");
- break;
- case APIC_INTERRUPT_COMMAND_HIGH:
- panic("Local APIC Interrupt Command high"
- " register unimplemented.\n");
- break;
case APIC_CURRENT_COUNT:
{
- assert(clock);
- uint32_t val = regs[reg] - curTick / clock;
- val /= (16 * divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
- return val;
+ if (apicTimerEvent.scheduled()) {
+ // Compute how many m5 ticks happen per count.
+ uint64_t ticksPerCount = clockPeriod() *
+ divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
+ // Compute how many m5 ticks are left.
+ uint64_t val = apicTimerEvent.when() - curTick();
+ // Turn that into a count.
+ val = (val + ticksPerCount - 1) / ticksPerCount;
+ return val;
+ } else {
+ return 0;
+ }
}
default:
break;
panic("Local APIC Processor Priority register unimplemented.\n");
break;
case APIC_EOI:
- panic("Local APIC EOI register unimplemented.\n");
- break;
+ // Remove the interrupt that just completed from the local apic state.
+ clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
+ updateISRV();
+ return;
case APIC_LOGICAL_DESTINATION:
newVal = val & 0xFF000000;
break;
}
break;
case APIC_INTERRUPT_COMMAND_LOW:
- panic("Local APIC Interrupt Command low"
- " register unimplemented.\n");
- break;
- case APIC_INTERRUPT_COMMAND_HIGH:
- panic("Local APIC Interrupt Command high"
- " register unimplemented.\n");
+ {
+ InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
+ // Check if we're already sending an IPI.
+ if (low.deliveryStatus) {
+ newVal = low;
+ break;
+ }
+ low = val;
+ InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
+ TriggerIntMessage message = 0;
+ message.destination = high.destination;
+ message.vector = low.vector;
+ message.deliveryMode = low.deliveryMode;
+ message.destMode = low.destMode;
+ message.level = low.level;
+ message.trigger = low.trigger;
+ std::list<int> apics;
+ int numContexts = sys->numContexts();
+ switch (low.destShorthand) {
+ case 0:
+ if (message.deliveryMode == DeliveryMode::LowestPriority) {
+ panic("Lowest priority delivery mode "
+ "IPIs aren't implemented.\n");
+ }
+ if (message.destMode == 1) {
+ int dest = message.destination;
+ hack_once("Assuming logical destinations are 1 << id.\n");
+ for (int i = 0; i < numContexts; i++) {
+ if (dest & 0x1)
+ apics.push_back(i);
+ dest = dest >> 1;
+ }
+ } else {
+ if (message.destination == 0xFF) {
+ for (int i = 0; i < numContexts; i++) {
+ if (i == initialApicId) {
+ requestInterrupt(message.vector,
+ message.deliveryMode, message.trigger);
+ } else {
+ apics.push_back(i);
+ }
+ }
+ } else {
+ if (message.destination == initialApicId) {
+ requestInterrupt(message.vector,
+ message.deliveryMode, message.trigger);
+ } else {
+ apics.push_back(message.destination);
+ }
+ }
+ }
+ break;
+ case 1:
+ newVal = val;
+ requestInterrupt(message.vector,
+ message.deliveryMode, message.trigger);
+ break;
+ case 2:
+ requestInterrupt(message.vector,
+ message.deliveryMode, message.trigger);
+ // Fall through
+ case 3:
+ {
+ for (int i = 0; i < numContexts; i++) {
+ if (i != initialApicId) {
+ apics.push_back(i);
+ }
+ }
+ }
+ break;
+ }
+ // Record that an IPI is being sent if one actually is.
+ if (apics.size()) {
+ low.deliveryStatus = 1;
+ pendingIPIs += apics.size();
+ }
+ regs[APIC_INTERRUPT_COMMAND_LOW] = low;
+ for (auto id: apics) {
+ PacketPtr pkt = buildIntTriggerPacket(id, message);
+ intMasterPort.sendMessage(pkt, sys->isTimingMode(),
+ [this](PacketPtr pkt) { completeIPI(pkt); });
+ }
+ newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
+ }
break;
case APIC_LVT_TIMER:
case APIC_LVT_THERMAL_SENSOR:
break;
case APIC_INITIAL_COUNT:
{
- assert(clock);
newVal = bits(val, 31, 0);
- uint32_t newCount = newVal *
- (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]) * 16);
- regs[APIC_CURRENT_COUNT] = newCount + curTick / clock;
- // Find out how long a "tick" of the timer should take.
- Tick timerTick = 16 * clock;
+ // Compute how many timer ticks we're being programmed for.
+ uint64_t newCount = newVal *
+ (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
// Schedule on the edge of the next tick plus the new count.
- Tick offset = curTick % timerTick;
+ Tick offset = curTick() % clockPeriod();
if (offset) {
reschedule(apicTimerEvent,
- curTick + (newCount + 1) * timerTick - offset, true);
+ curTick() + (newCount + 1) *
+ clockPeriod() - offset, true);
} else {
- reschedule(apicTimerEvent,
- curTick + newCount * timerTick, true);
+ if (newCount)
+ reschedule(apicTimerEvent,
+ curTick() + newCount *
+ clockPeriod(), true);
}
}
break;
return;
}
+
+X86ISA::Interrupts::Interrupts(Params * p)
+ : BaseInterrupts(p), sys(p->system), clockDomain(*p->clk_domain),
+ apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
+ pendingSmi(false), smiVector(0),
+ pendingNmi(false), nmiVector(0),
+ pendingExtInt(false), extIntVector(0),
+ pendingInit(false), initVector(0),
+ pendingStartup(false), startupVector(0),
+ startedUp(false), pendingUnmaskableInt(false),
+ pendingIPIs(0), cpu(NULL),
+ intSlavePort(name() + ".int_slave", this, this),
+ intMasterPort(name() + ".int_master", this, this, p->int_latency),
+ pioPort(this), pioDelay(p->pio_latency)
+{
+ memset(regs, 0, sizeof(regs));
+ //Set the local apic DFR to the flat model.
+ regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
+ ISRV = 0;
+ IRRV = 0;
+
+ regs[APIC_VERSION] = (5 << 16) | 0x14;
+}
+
+
+bool
+X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
+{
+ RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
+ if (pendingUnmaskableInt) {
+ DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
+ return true;
+ }
+ if (rflags.intf) {
+ if (pendingExtInt) {
+ DPRINTF(LocalApic, "Reported pending external interrupt.\n");
+ return true;
+ }
+ if (IRRV > ISRV && bits(IRRV, 7, 4) >
+ bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
+ DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
+ return true;
+ }
+ }
+ return false;
+}
+
+bool
+X86ISA::Interrupts::checkInterruptsRaw() const
+{
+ return pendingUnmaskableInt || pendingExtInt ||
+ (IRRV > ISRV && bits(IRRV, 7, 4) >
+ bits(regs[APIC_TASK_PRIORITY], 7, 4));
+}
+
+Fault
+X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
+{
+ assert(checkInterrupts(tc));
+ // These are all probably fairly uncommon, so we'll make them easier to
+ // check for.
+ if (pendingUnmaskableInt) {
+ if (pendingSmi) {
+ DPRINTF(LocalApic, "Generated SMI fault object.\n");
+ return std::make_shared<SystemManagementInterrupt>();
+ } else if (pendingNmi) {
+ DPRINTF(LocalApic, "Generated NMI fault object.\n");
+ return std::make_shared<NonMaskableInterrupt>(nmiVector);
+ } else if (pendingInit) {
+ DPRINTF(LocalApic, "Generated INIT fault object.\n");
+ return std::make_shared<InitInterrupt>(initVector);
+ } else if (pendingStartup) {
+ DPRINTF(LocalApic, "Generating SIPI fault object.\n");
+ return std::make_shared<StartupInterrupt>(startupVector);
+ } else {
+ panic("pendingUnmaskableInt set, but no unmaskable "
+ "ints were pending.\n");
+ return NoFault;
+ }
+ } else if (pendingExtInt) {
+ DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
+ return std::make_shared<ExternalInterrupt>(extIntVector);
+ } else {
+ DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
+ // The only thing left are fixed and lowest priority interrupts.
+ return std::make_shared<ExternalInterrupt>(IRRV);
+ }
+}
+
+void
+X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
+{
+ assert(checkInterrupts(tc));
+ if (pendingUnmaskableInt) {
+ if (pendingSmi) {
+ DPRINTF(LocalApic, "SMI sent to core.\n");
+ pendingSmi = false;
+ } else if (pendingNmi) {
+ DPRINTF(LocalApic, "NMI sent to core.\n");
+ pendingNmi = false;
+ } else if (pendingInit) {
+ DPRINTF(LocalApic, "Init sent to core.\n");
+ pendingInit = false;
+ startedUp = false;
+ } else if (pendingStartup) {
+ DPRINTF(LocalApic, "SIPI sent to core.\n");
+ pendingStartup = false;
+ startedUp = true;
+ }
+ if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
+ pendingUnmaskableInt = false;
+ } else if (pendingExtInt) {
+ pendingExtInt = false;
+ } else {
+ DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
+ // Mark the interrupt as "in service".
+ ISRV = IRRV;
+ setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
+ // Clear it out of the IRR.
+ clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
+ updateIRRV();
+ }
+}
+
+void
+X86ISA::Interrupts::serialize(CheckpointOut &cp) const
+{
+ SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
+ SERIALIZE_SCALAR(pendingSmi);
+ SERIALIZE_SCALAR(smiVector);
+ SERIALIZE_SCALAR(pendingNmi);
+ SERIALIZE_SCALAR(nmiVector);
+ SERIALIZE_SCALAR(pendingExtInt);
+ SERIALIZE_SCALAR(extIntVector);
+ SERIALIZE_SCALAR(pendingInit);
+ SERIALIZE_SCALAR(initVector);
+ SERIALIZE_SCALAR(pendingStartup);
+ SERIALIZE_SCALAR(startupVector);
+ SERIALIZE_SCALAR(startedUp);
+ SERIALIZE_SCALAR(pendingUnmaskableInt);
+ SERIALIZE_SCALAR(pendingIPIs);
+ SERIALIZE_SCALAR(IRRV);
+ SERIALIZE_SCALAR(ISRV);
+ bool apicTimerEventScheduled = apicTimerEvent.scheduled();
+ SERIALIZE_SCALAR(apicTimerEventScheduled);
+ Tick apicTimerEventTick = apicTimerEvent.when();
+ SERIALIZE_SCALAR(apicTimerEventTick);
+}
+
+void
+X86ISA::Interrupts::unserialize(CheckpointIn &cp)
+{
+ UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
+ UNSERIALIZE_SCALAR(pendingSmi);
+ UNSERIALIZE_SCALAR(smiVector);
+ UNSERIALIZE_SCALAR(pendingNmi);
+ UNSERIALIZE_SCALAR(nmiVector);
+ UNSERIALIZE_SCALAR(pendingExtInt);
+ UNSERIALIZE_SCALAR(extIntVector);
+ UNSERIALIZE_SCALAR(pendingInit);
+ UNSERIALIZE_SCALAR(initVector);
+ UNSERIALIZE_SCALAR(pendingStartup);
+ UNSERIALIZE_SCALAR(startupVector);
+ UNSERIALIZE_SCALAR(startedUp);
+ UNSERIALIZE_SCALAR(pendingUnmaskableInt);
+ UNSERIALIZE_SCALAR(pendingIPIs);
+ UNSERIALIZE_SCALAR(IRRV);
+ UNSERIALIZE_SCALAR(ISRV);
+ bool apicTimerEventScheduled;
+ UNSERIALIZE_SCALAR(apicTimerEventScheduled);
+ if (apicTimerEventScheduled) {
+ Tick apicTimerEventTick;
+ UNSERIALIZE_SCALAR(apicTimerEventTick);
+ if (apicTimerEvent.scheduled()) {
+ reschedule(apicTimerEvent, apicTimerEventTick, true);
+ } else {
+ schedule(apicTimerEvent, apicTimerEventTick);
+ }
+ }
+}
+
X86ISA::Interrupts *
X86LocalApicParams::create()
{
return new X86ISA::Interrupts(this);
}
+
+void
+X86ISA::Interrupts::processApicTimerEvent() {
+ if (triggerTimerInterrupt())
+ setReg(APIC_INITIAL_COUNT, readReg(APIC_INITIAL_COUNT));
+}
projects / gem5.git / blobdiff