/*
- * Copyright (c) 2008 The Hewlett-Packard Development Company
- * All rights reserved.
+ * Copyright (c) 2012-2013 ARM Limited
+ * All rights reserved
*
- * Redistribution and use of this software in source and binary forms,
- * with or without modification, are permitted provided that the
- * following conditions are met:
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
*
- * The software must be used only for Non-Commercial Use which means any
- * use which is NOT directed to receiving any direct monetary
- * compensation for, or commercial advantage from such use. Illustrative
- * examples of non-commercial use are academic research, personal study,
- * teaching, education and corporate research & development.
- * Illustrative examples of commercial use are distributing products for
- * commercial advantage and providing services using the software for
- * commercial advantage.
+ * Copyright (c) 2008 The Hewlett-Packard Development Company
+ * All rights reserved.
*
- * If you wish to use this software or functionality therein that may be
- * covered by patents for commercial use, please contact:
- * Director of Intellectual Property Licensing
- * Office of Strategy and Technology
- * Hewlett-Packard Company
- * 1501 Page Mill Road
- * Palo Alto, California 94304
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
*
- * Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer. Redistributions
- * in binary form must reproduce the above copyright notice, this list of
- * conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution. Neither the name of
- * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission. No right of
- * sublicense is granted herewith. Derivatives of the software and
- * output created using the software may be prepared, but only for
- * Non-Commercial Uses. Derivatives of the software may be shared with
- * others provided: (i) the others agree to abide by the list of
- * conditions herein which includes the Non-Commercial Use restrictions;
- * and (ii) such Derivatives of the software include the above copyright
- * notice to acknowledge the contribution from this software where
- * applicable, this list of conditions and the disclaimer below.
+ * this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Authors: Gabe Black
*/
-#include "arch/x86/apicregs.hh"
#include "arch/x86/interrupts.hh"
+
+#include <list>
+#include <memory>
+
#include "arch/x86/intmessage.hh"
+#include "arch/x86/regs/apic.hh"
#include "cpu/base.hh"
+#include "debug/LocalApic.hh"
+#include "dev/x86/i82094aa.hh"
+#include "dev/x86/pc.hh"
+#include "dev/x86/south_bridge.hh"
#include "mem/packet_access.hh"
+#include "sim/full_system.hh"
#include "sim/system.hh"
int
regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
break;
case 0x100:
- case 0x108:
case 0x110:
- case 0x118:
case 0x120:
- case 0x128:
case 0x130:
- case 0x138:
case 0x140:
- case 0x148:
case 0x150:
- case 0x158:
case 0x160:
- case 0x168:
case 0x170:
- case 0x178:
- regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
+ regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x10);
break;
case 0x180:
- case 0x188:
case 0x190:
- case 0x198:
case 0x1A0:
- case 0x1A8:
case 0x1B0:
- case 0x1B8:
case 0x1C0:
- case 0x1C8:
case 0x1D0:
- case 0x1D8:
case 0x1E0:
- case 0x1E8:
case 0x1F0:
- case 0x1F8:
- regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
+ regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x10);
break;
case 0x200:
- case 0x208:
case 0x210:
- case 0x218:
case 0x220:
- case 0x228:
case 0x230:
- case 0x238:
case 0x240:
- case 0x248:
case 0x250:
- case 0x258:
case 0x260:
- case 0x268:
case 0x270:
- case 0x278:
- regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
+ regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x10);
break;
case 0x280:
regNum = APIC_ERROR_STATUS;
X86ISA::Interrupts::read(PacketPtr pkt)
{
Addr offset = pkt->getAddr() - pioAddr;
- //Make sure we're at least only accessing one register.
+ // Make sure we're at least only accessing one register.
if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
panic("Accessed more than one register at a time in the APIC!\n");
ApicRegIndex reg = decodeAddr(offset);
- uint32_t val = htog(readReg(reg));
+ uint32_t val = htole(readReg(reg));
DPRINTF(LocalApic,
"Reading Local APIC register %d at offset %#x as %#x.\n",
reg, offset, val);
pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
pkt->makeAtomicResponse();
- return latency;
+ return pioDelay;
}
Tick
X86ISA::Interrupts::write(PacketPtr pkt)
{
Addr offset = pkt->getAddr() - pioAddr;
- //Make sure we're at least only accessing one register.
+ // Make sure we're at least only accessing one register.
if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
panic("Accessed more than one register at a time in the APIC!\n");
ApicRegIndex reg = decodeAddr(offset);
pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
DPRINTF(LocalApic,
"Writing Local APIC register %d at offset %#x as %#x.\n",
- reg, offset, gtoh(val));
- setReg(reg, gtoh(val));
+ reg, offset, letoh(val));
+ setReg(reg, letoh(val));
pkt->makeAtomicResponse();
- return latency;
+ return pioDelay;
}
void
X86ISA::Interrupts::requestInterrupt(uint8_t vector,
pendingUnmaskableInt = pendingStartup = true;
startupVector = vector;
}
- }
- cpu->wakeup();
+ }
+ if (FullSystem)
+ cpu->wakeup(0);
}
void
X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
{
+ assert(newCPU);
+ if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
+ panic("Local APICs can't be moved between CPUs"
+ " with different IDs.\n");
+ }
cpu = newCPU;
- assert(cpu);
- regs[APIC_ID] = (cpu->cpuId() << 24);
+ initialApicId = cpu->cpuId();
+ regs[APIC_ID] = (initialApicId << 24);
+ pioAddr = x86LocalAPICAddress(initialApicId, 0);
+}
+
+
+void
+X86ISA::Interrupts::init()
+{
+ panic_if(!intMasterPort.isConnected(),
+ "Int port not connected to anything!");
+ panic_if(!pioPort.isConnected(),
+ "Pio port of %s not connected to anything!", name());
+
+ intSlavePort.sendRangeChange();
+ pioPort.sendRangeChange();
}
Tick
X86ISA::Interrupts::recvMessage(PacketPtr pkt)
{
- uint8_t id = (regs[APIC_ID] >> 24);
- Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0);
- assert(pkt->cmd == MemCmd::MessageReq);
+ Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
+ assert(pkt->cmd == MemCmd::WriteReq);
switch(offset)
{
case 0:
{
- TriggerIntMessage message = pkt->get<TriggerIntMessage>();
+ TriggerIntMessage message = pkt->getRaw<TriggerIntMessage>();
DPRINTF(LocalApic,
"Got Trigger Interrupt message with vector %#x.\n",
message.vector);
- // Make sure we're really supposed to get this.
- assert((message.destMode == 0 && message.destination == id) ||
- (bits((int)message.destination, id)));
requestInterrupt(message.vector,
message.deliveryMode, message.trigger);
break;
}
pkt->makeAtomicResponse();
- return latency;
+ return pioDelay;
}
-Tick
-X86ISA::Interrupts::recvResponse(PacketPtr pkt)
+void
+X86ISA::Interrupts::completeIPI(PacketPtr pkt)
{
- assert(!pkt->isError());
- assert(pkt->cmd == MemCmd::MessageResp);
if (--pendingIPIs == 0) {
InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
// Record that the ICR is now idle.
low.deliveryStatus = 0;
regs[APIC_INTERRUPT_COMMAND_LOW] = low;
}
- delete pkt->req;
- delete pkt;
DPRINTF(LocalApic, "ICR is now idle.\n");
- return 0;
+ delete pkt;
}
-void
-X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
+AddrRangeList
+X86ISA::Interrupts::getAddrRanges() const
{
- uint8_t id = (regs[APIC_ID] >> 24);
- range_list.clear();
- Range<Addr> range = RangeEx(x86LocalAPICAddress(id, 0),
- x86LocalAPICAddress(id, 0) + PageBytes);
- range_list.push_back(range);
- pioAddr = range.start;
+ assert(cpu);
+ AddrRangeList ranges;
+ ranges.push_back(RangeSize(pioAddr, PageBytes));
+ return ranges;
}
-void
-X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list)
+AddrRangeList
+X86ISA::Interrupts::getIntAddrRange() const
{
- uint8_t id = (regs[APIC_ID] >> 24);
- range_list.clear();
- range_list.push_back(RangeEx(x86InterruptAddress(id, 0),
- x86InterruptAddress(id, 0) + PhysAddrAPICRangeSize));
+ AddrRangeList ranges;
+ ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
+ x86InterruptAddress(initialApicId, 0) +
+ PhysAddrAPICRangeSize));
+ return ranges;
}
case APIC_CURRENT_COUNT:
{
if (apicTimerEvent.scheduled()) {
- assert(clock);
// Compute how many m5 ticks happen per count.
- uint64_t ticksPerCount = clock *
+ uint64_t ticksPerCount = clockPeriod() *
divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
// Compute how many m5 ticks are left.
- uint64_t val = apicTimerEvent.when() - curTick;
+ uint64_t val = apicTimerEvent.when() - curTick();
// Turn that into a count.
val = (val + ticksPerCount - 1) / ticksPerCount;
return val;
}
low = val;
InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
- // Record that an IPI is being sent.
- low.deliveryStatus = 1;
- TriggerIntMessage message;
+ TriggerIntMessage message = 0;
message.destination = high.destination;
message.vector = low.vector;
message.deliveryMode = low.deliveryMode;
message.destMode = low.destMode;
message.level = low.level;
message.trigger = low.trigger;
- bool timing = sys->getMemoryMode() == Enums::timing;
- // Be careful no updates of the delivery status bit get lost.
- regs[APIC_INTERRUPT_COMMAND_LOW] = low;
+ std::list<int> apics;
+ int numContexts = sys->numContexts();
switch (low.destShorthand) {
case 0:
- pendingIPIs++;
- intPort->sendMessage(message, timing);
- newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
+ if (message.deliveryMode == DeliveryMode::LowestPriority) {
+ panic("Lowest priority delivery mode "
+ "IPIs aren't implemented.\n");
+ }
+ if (message.destMode == 1) {
+ int dest = message.destination;
+ hack_once("Assuming logical destinations are 1 << id.\n");
+ for (int i = 0; i < numContexts; i++) {
+ if (dest & 0x1)
+ apics.push_back(i);
+ dest = dest >> 1;
+ }
+ } else {
+ if (message.destination == 0xFF) {
+ for (int i = 0; i < numContexts; i++) {
+ if (i == initialApicId) {
+ requestInterrupt(message.vector,
+ message.deliveryMode, message.trigger);
+ } else {
+ apics.push_back(i);
+ }
+ }
+ } else {
+ if (message.destination == initialApicId) {
+ requestInterrupt(message.vector,
+ message.deliveryMode, message.trigger);
+ } else {
+ apics.push_back(message.destination);
+ }
+ }
+ }
break;
case 1:
newVal = val;
// Fall through
case 3:
{
- int numContexts = sys->numContexts();
- pendingIPIs += (numContexts - 1);
- // We have no way to get at the thread context we're part
- // of, so we'll just have to go with the CPU for now.
- hack_once("Broadcast IPIs can't handle more than "
- "one context per CPU.\n");
- int myId = cpu->getContext(0)->contextId();
for (int i = 0; i < numContexts; i++) {
- int thisId = sys->getThreadContext(i)->contextId();
- if (thisId != myId) {
- PacketPtr pkt = buildIntRequest(thisId, message);
- if (timing)
- intPort->sendMessageTiming(pkt, latency);
- else
- intPort->sendMessageAtomic(pkt);
+ if (i != initialApicId) {
+ apics.push_back(i);
}
}
}
- newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
break;
}
+ // Record that an IPI is being sent if one actually is.
+ if (apics.size()) {
+ low.deliveryStatus = 1;
+ pendingIPIs += apics.size();
+ }
+ regs[APIC_INTERRUPT_COMMAND_LOW] = low;
+ for (auto id: apics) {
+ PacketPtr pkt = buildIntTriggerPacket(id, message);
+ intMasterPort.sendMessage(pkt, sys->isTimingMode(),
+ [this](PacketPtr pkt) { completeIPI(pkt); });
+ }
+ newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
}
break;
case APIC_LVT_TIMER:
break;
case APIC_INITIAL_COUNT:
{
- assert(clock);
newVal = bits(val, 31, 0);
// Compute how many timer ticks we're being programmed for.
uint64_t newCount = newVal *
(divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
// Schedule on the edge of the next tick plus the new count.
- Tick offset = curTick % clock;
+ Tick offset = curTick() % clockPeriod();
if (offset) {
reschedule(apicTimerEvent,
- curTick + (newCount + 1) * clock - offset, true);
+ curTick() + (newCount + 1) *
+ clockPeriod() - offset, true);
} else {
- reschedule(apicTimerEvent,
- curTick + newCount * clock, true);
+ if (newCount)
+ reschedule(apicTimerEvent,
+ curTick() + newCount *
+ clockPeriod(), true);
}
}
break;
}
-X86ISA::Interrupts::Interrupts(Params * p) :
- BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
- apicTimerEvent(this),
- pendingSmi(false), smiVector(0),
- pendingNmi(false), nmiVector(0),
- pendingExtInt(false), extIntVector(0),
- pendingInit(false), initVector(0),
- pendingStartup(false), startupVector(0),
- startedUp(false), pendingUnmaskableInt(false),
- pendingIPIs(0)
+X86ISA::Interrupts::Interrupts(Params * p)
+ : BaseInterrupts(p), sys(p->system), clockDomain(*p->clk_domain),
+ apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
+ pendingSmi(false), smiVector(0),
+ pendingNmi(false), nmiVector(0),
+ pendingExtInt(false), extIntVector(0),
+ pendingInit(false), initVector(0),
+ pendingStartup(false), startupVector(0),
+ startedUp(false), pendingUnmaskableInt(false),
+ pendingIPIs(0), cpu(NULL),
+ intSlavePort(name() + ".int_slave", this, this),
+ intMasterPort(name() + ".int_master", this, this, p->int_latency),
+ pioPort(this), pioDelay(p->pio_latency)
{
- pioSize = PageBytes;
memset(regs, 0, sizeof(regs));
//Set the local apic DFR to the flat model.
regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
ISRV = 0;
IRRV = 0;
+
+ regs[APIC_VERSION] = (5 << 16) | 0x14;
}
return false;
}
+bool
+X86ISA::Interrupts::checkInterruptsRaw() const
+{
+ return pendingUnmaskableInt || pendingExtInt ||
+ (IRRV > ISRV && bits(IRRV, 7, 4) >
+ bits(regs[APIC_TASK_PRIORITY], 7, 4));
+}
+
Fault
X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
{
if (pendingUnmaskableInt) {
if (pendingSmi) {
DPRINTF(LocalApic, "Generated SMI fault object.\n");
- return new SystemManagementInterrupt();
+ return std::make_shared<SystemManagementInterrupt>();
} else if (pendingNmi) {
DPRINTF(LocalApic, "Generated NMI fault object.\n");
- return new NonMaskableInterrupt(nmiVector);
+ return std::make_shared<NonMaskableInterrupt>(nmiVector);
} else if (pendingInit) {
DPRINTF(LocalApic, "Generated INIT fault object.\n");
- return new InitInterrupt(initVector);
+ return std::make_shared<InitInterrupt>(initVector);
} else if (pendingStartup) {
DPRINTF(LocalApic, "Generating SIPI fault object.\n");
- return new StartupInterrupt(startupVector);
+ return std::make_shared<StartupInterrupt>(startupVector);
} else {
panic("pendingUnmaskableInt set, but no unmaskable "
"ints were pending.\n");
}
} else if (pendingExtInt) {
DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
- return new ExternalInterrupt(extIntVector);
+ return std::make_shared<ExternalInterrupt>(extIntVector);
} else {
DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
// The only thing left are fixed and lowest priority interrupts.
- return new ExternalInterrupt(IRRV);
+ return std::make_shared<ExternalInterrupt>(IRRV);
}
}
}
}
+void
+X86ISA::Interrupts::serialize(CheckpointOut &cp) const
+{
+ SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
+ SERIALIZE_SCALAR(pendingSmi);
+ SERIALIZE_SCALAR(smiVector);
+ SERIALIZE_SCALAR(pendingNmi);
+ SERIALIZE_SCALAR(nmiVector);
+ SERIALIZE_SCALAR(pendingExtInt);
+ SERIALIZE_SCALAR(extIntVector);
+ SERIALIZE_SCALAR(pendingInit);
+ SERIALIZE_SCALAR(initVector);
+ SERIALIZE_SCALAR(pendingStartup);
+ SERIALIZE_SCALAR(startupVector);
+ SERIALIZE_SCALAR(startedUp);
+ SERIALIZE_SCALAR(pendingUnmaskableInt);
+ SERIALIZE_SCALAR(pendingIPIs);
+ SERIALIZE_SCALAR(IRRV);
+ SERIALIZE_SCALAR(ISRV);
+ bool apicTimerEventScheduled = apicTimerEvent.scheduled();
+ SERIALIZE_SCALAR(apicTimerEventScheduled);
+ Tick apicTimerEventTick = apicTimerEvent.when();
+ SERIALIZE_SCALAR(apicTimerEventTick);
+}
+
+void
+X86ISA::Interrupts::unserialize(CheckpointIn &cp)
+{
+ UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
+ UNSERIALIZE_SCALAR(pendingSmi);
+ UNSERIALIZE_SCALAR(smiVector);
+ UNSERIALIZE_SCALAR(pendingNmi);
+ UNSERIALIZE_SCALAR(nmiVector);
+ UNSERIALIZE_SCALAR(pendingExtInt);
+ UNSERIALIZE_SCALAR(extIntVector);
+ UNSERIALIZE_SCALAR(pendingInit);
+ UNSERIALIZE_SCALAR(initVector);
+ UNSERIALIZE_SCALAR(pendingStartup);
+ UNSERIALIZE_SCALAR(startupVector);
+ UNSERIALIZE_SCALAR(startedUp);
+ UNSERIALIZE_SCALAR(pendingUnmaskableInt);
+ UNSERIALIZE_SCALAR(pendingIPIs);
+ UNSERIALIZE_SCALAR(IRRV);
+ UNSERIALIZE_SCALAR(ISRV);
+ bool apicTimerEventScheduled;
+ UNSERIALIZE_SCALAR(apicTimerEventScheduled);
+ if (apicTimerEventScheduled) {
+ Tick apicTimerEventTick;
+ UNSERIALIZE_SCALAR(apicTimerEventTick);
+ if (apicTimerEvent.scheduled()) {
+ reschedule(apicTimerEvent, apicTimerEventTick, true);
+ } else {
+ schedule(apicTimerEvent, apicTimerEventTick);
+ }
+ }
+}
+
X86ISA::Interrupts *
X86LocalApicParams::create()
{
return new X86ISA::Interrupts(this);
}
+
+void
+X86ISA::Interrupts::processApicTimerEvent() {
+ if (triggerTimerInterrupt())
+ setReg(APIC_INITIAL_COUNT, readReg(APIC_INITIAL_COUNT));
+}
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