#ifndef __ARCH_X86_INTERRUPTS_HH__
#define __ARCH_X86_INTERRUPTS_HH__
+#include "arch/x86/apicregs.hh"
#include "arch/x86/faults.hh"
+#include "arch/x86/intmessage.hh"
+#include "base/bitfield.hh"
#include "cpu/thread_context.hh"
+#include "dev/io_device.hh"
+#include "dev/x86/intdev.hh"
+#include "params/X86LocalApic.hh"
+#include "sim/eventq.hh"
-namespace X86ISA
-{
+class ThreadContext;
+class BaseCPU;
+
+namespace X86ISA {
-class Interrupts
+class Interrupts : public BasicPioDevice, IntDev
{
- public:
- Interrupts()
+ protected:
+ // Storage for the APIC registers
+ uint32_t regs[NUM_APIC_REGS];
+
+ BitUnion32(LVTEntry)
+ Bitfield<7, 0> vector;
+ Bitfield<10, 8> deliveryMode;
+ Bitfield<12> status;
+ Bitfield<13> polarity;
+ Bitfield<14> remoteIRR;
+ Bitfield<15> trigger;
+ Bitfield<16> masked;
+ Bitfield<17> periodic;
+ EndBitUnion(LVTEntry)
+
+ /*
+ * Timing related stuff.
+ */
+ Tick latency;
+ Tick clock;
+
+ class ApicTimerEvent : public Event
{
- clear_all();
- }
+ private:
+ Interrupts *localApic;
+ public:
+ ApicTimerEvent(Interrupts *_localApic) :
+ Event(), localApic(_localApic)
+ {}
+
+ void process()
+ {
+ assert(localApic);
+ if (localApic->triggerTimerInterrupt()) {
+ localApic->setReg(APIC_INITIAL_COUNT,
+ localApic->readReg(APIC_INITIAL_COUNT));
+ }
+ }
+ };
+
+ ApicTimerEvent apicTimerEvent;
+
+ /*
+ * A set of variables to keep track of interrupts that don't go through
+ * the IRR.
+ */
+ bool pendingSmi;
+ uint8_t smiVector;
+ bool pendingNmi;
+ uint8_t nmiVector;
+ bool pendingExtInt;
+ uint8_t extIntVector;
+ bool pendingInit;
+ uint8_t initVector;
+ bool pendingStartup;
+ uint8_t startupVector;
+ bool startedUp;
+
+ // This is a quick check whether any of the above (except ExtInt) are set.
+ bool pendingUnmaskableInt;
+
+ // A count of how many IPIs are in flight.
+ int pendingIPIs;
+
+ /*
+ * IRR and ISR maintenance.
+ */
+ uint8_t IRRV;
+ uint8_t ISRV;
- int InterruptLevel(uint64_t softint)
+ int
+ findRegArrayMSB(ApicRegIndex base)
{
- panic("Interrupts::InterruptLevel unimplemented!\n");
+ int offset = 7;
+ do {
+ if (regs[base + offset] != 0) {
+ return offset * 32 + findMsbSet(regs[base + offset]);
+ }
+ } while (offset--);
return 0;
}
- void post(int int_num, int index)
+ void
+ updateIRRV()
{
- panic("Interrupts::post unimplemented!\n");
+ IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
+ }
+
+ void
+ updateISRV()
+ {
+ ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
+ }
+
+ void
+ setRegArrayBit(ApicRegIndex base, uint8_t vector)
+ {
+ regs[base + (vector / 32)] |= (1 << (vector % 32));
+ }
+
+ void
+ clearRegArrayBit(ApicRegIndex base, uint8_t vector)
+ {
+ regs[base + (vector / 32)] &= ~(1 << (vector % 32));
+ }
+
+ bool
+ getRegArrayBit(ApicRegIndex base, uint8_t vector)
+ {
+ return bits(regs[base + (vector / 32)], vector % 5);
}
- void clear(int int_num, int index)
+ void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
+
+ BaseCPU *cpu;
+
+ int initialApicId;
+
+ public:
+ /*
+ * Params stuff.
+ */
+ typedef X86LocalApicParams Params;
+
+ void setCPU(BaseCPU * newCPU);
+
+ void
+ setClock(Tick newClock)
{
- warn("Interrupts::clear unimplemented!\n");
+ clock = newClock;
}
- void clear_all()
+ const Params *
+ params() const
{
- warn("Interrupts::clear_all unimplemented!\n");
+ return dynamic_cast<const Params *>(_params);
}
- bool check_interrupts(ThreadContext * tc) const
+ /*
+ * Initialize this object by registering it with the IO APIC.
+ */
+ void init();
+
+ /*
+ * Functions to interact with the interrupt port from IntDev.
+ */
+ Tick read(PacketPtr pkt);
+ Tick write(PacketPtr pkt);
+ Tick recvMessage(PacketPtr pkt);
+ Tick recvResponse(PacketPtr pkt);
+
+ bool
+ triggerTimerInterrupt()
{
- return false;
+ LVTEntry entry = regs[APIC_LVT_TIMER];
+ if (!entry.masked)
+ requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
+ return entry.periodic;
}
- Fault getInterrupt(ThreadContext * tc)
+ void addressRanges(AddrRangeList &range_list);
+ void getIntAddrRange(AddrRangeList &range_list);
+
+ Port *getPort(const std::string &if_name, int idx = -1)
{
- return NoFault;
+ if (if_name == "int_port")
+ return intPort;
+ return BasicPioDevice::getPort(if_name, idx);
}
- void updateIntrInfo(ThreadContext * tc)
+ /*
+ * Functions to access and manipulate the APIC's registers.
+ */
+
+ uint32_t readReg(ApicRegIndex miscReg);
+ void setReg(ApicRegIndex reg, uint32_t val);
+ void
+ setRegNoEffect(ApicRegIndex reg, uint32_t val)
{
- panic("Interrupts::updateIntrInfo unimplemented!\n");
+ regs[reg] = val;
}
- void serialize(std::ostream & os)
+ /*
+ * Constructor.
+ */
+
+ Interrupts(Params * p);
+
+ /*
+ * Functions for retrieving interrupts for the CPU to handle.
+ */
+
+ bool checkInterrupts(ThreadContext *tc) const;
+ Fault getInterrupt(ThreadContext *tc);
+ void updateIntrInfo(ThreadContext *tc);
+
+ /*
+ * Serialization.
+ */
+
+ void
+ serialize(std::ostream &os)
{
panic("Interrupts::serialize unimplemented!\n");
}
- void unserialize(Checkpoint * cp, const std::string & section)
+ void
+ unserialize(Checkpoint *cp, const std::string §ion)
{
panic("Interrupts::unserialize unimplemented!\n");
}
-};
+ /*
+ * Old functions needed for compatability but which will be phased out
+ * eventually.
+ */
+ void
+ post(int int_num, int index)
+ {
+ panic("Interrupts::post unimplemented!\n");
+ }
+
+ void
+ clear(int int_num, int index)
+ {
+ panic("Interrupts::clear unimplemented!\n");
+ }
+
+ void
+ clearAll()
+ {
+ panic("Interrupts::clearAll unimplemented!\n");
+ }
};
+} // namespace X86ISA
+
#endif // __ARCH_X86_INTERRUPTS_HH__
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