X86: Hook in the M5 pseudo insts.

[gem5.git] / src / arch / x86 / isa / decoder / two_byte_opcodes.isa

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index b8013165ee97dc5ceb03de3b86a973d47722597a..4ebe03d84fb7d76f4f78f9a02f33fddf04defacb 100644 (file)
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -163,8 +163,96 @@
                 }
                 0x02: lar_Gv_Ew();
                 0x03: lsl_Gv_Ew();
-                //sandpile.org doesn't seem to know what this is... ?
-                0x04: loadall_or_reset_or_hang();
+                // sandpile.org doesn't seem to know what this is...? We'll
+                // use it for pseudo instructions. We've got 16 bits of space
+                // to play with so there can be quite a few pseudo
+                // instructions.
+                //0x04: loadall_or_reset_or_hang();
+                0x4: decode IMMEDIATE {
+                    format BasicOperate {
+#if FULL_SYSTEM
+                        0x00: m5arm({{
+                            PseudoInst::arm(xc->tcBase());
+                        }}, IsNonSpeculative);
+                        0x01: m5quiesce({{
+                            PseudoInst::quiesce(xc->tcBase());
+                        }}, IsNonSpeculative);
+                        0x02: m5quiesceNs({{
+                            PseudoInst::quiesceNs(xc->tcBase(), Rdi);
+                        }}, IsNonSpeculative);
+                        0x03: m5quiesceCycle({{
+                            PseudoInst::quiesceCycles(xc->tcBase(), Rdi);
+                        }}, IsNonSpeculative);
+                        0x04: m5quiesceTime({{
+                            Rax = PseudoInst::quiesceTime(xc->tcBase());
+                        }}, IsNonSpeculative);
+#endif
+                        0x07: m5rpns({{
+                            Rax = PseudoInst::rpns(xc->tcBase());
+                        }}, IsNonSpeculative);
+                        0x21: m5exit({{
+                            PseudoInst::m5exit(xc->tcBase(), Rdi);
+                        }}, IsNonSpeculative);
+#if FULL_SYSTEM
+                        0x30: m5initparam({{
+                            Rax = xc->tcBase()->getCpuPtr()->
+                                      system->init_param;
+                        }}, IsNonSpeculative);
+                        0x31: m5loadsymbol({{
+                            PseudoInst::loadsymbol(xc->tcBase());
+                        }}, IsNonSpeculative);
+#endif
+                        0x40: m5resetstats({{
+                            PseudoInst::resetstats(xc->tcBase(), Rdi, Rsi);
+                        }}, IsNonSpeculative);
+                        0x41: m5dumpstats({{
+                            PseudoInst::dumpstats(xc->tcBase(), Rdi, Rsi);
+                        }}, IsNonSpeculative);
+                        0x42: m5dumpresetstats({{
+                            PseudoInst::dumpresetstats(xc->tcBase(), Rdi, Rsi);
+                        }}, IsNonSpeculative);
+                        0x43: m5checkpoint({{
+                            PseudoInst::m5checkpoint(xc->tcBase(), Rdi, Rsi);
+                        }}, IsNonSpeculative);
+#if FULL_SYSTEM
+                        0x50: m5readfile({{
+                            Rax = PseudoInst::readfile(
+                                xc->tcBase(), Rdi, Rsi, Rdx);
+                        }}, IsNonSpeculative);
+#endif
+                        0x51: m5debugbreak({{
+                            PseudoInst::debugbreak(xc->tcBase());
+                        }}, IsNonSpeculative);
+                        0x52: m5switchcpu({{
+                            PseudoInst::switchcpu(xc->tcBase());
+                        }}, IsNonSpeculative);
+#if FULL_SYSTEM
+                        0x53: m5addsymbol({{
+                            PseudoInst::addsymbol(xc->tcBase(), Rdi, Rsi);
+                        }}, IsNonSpeculative);
+#endif
+                        0x54: m5panic({{
+                            panic("M5 panic instruction called at pc=%#x.\n",
+                                xc->readPC());
+                        }}, IsNonSpeculative);
+                        0x55: m5reserved1({{
+                            warn("M5 reserved opcode 1 ignored.\n");
+                        }}, IsNonSpeculative);
+                        0x56: m5reserved2({{
+                            warn("M5 reserved opcode 2 ignored.\n");
+                        }}, IsNonSpeculative);
+                        0x57: m5reserved3({{
+                            warn("M5 reserved opcode 3 ignored.\n");
+                        }}, IsNonSpeculative);
+                        0x58: m5reserved4({{
+                            warn("M5 reserved opcode 4 ignored.\n");
+                        }}, IsNonSpeculative);
+                        0x59: m5reserved5({{
+                            warn("M5 reserved opcode 5 ignored.\n");
+                        }}, IsNonSpeculative);
+                        default: Inst::UD2();
+                    }
+                }
 #if FULL_SYSTEM
                 0x05: syscall();
 #else