arch-x86: fix CondInst decoding for MOV to Control Registers

[gem5.git] / src / arch / x86 / isa / decoder / two_byte_opcodes.isa

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 8b875682303f0d1e55eba33a6288abb1f292226e..f0698ce18386bc3f048062411335ba12493428d6 100644 (file)
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -361,7 +361,7 @@
                 // no prefix
                 0x0: decode OPCODE_OP_BOTTOM3 {
                     0x0: CondInst::MOV(
-                        {{isValidMiscReg(MISCREG_CR(MODRM_RM))}},Rd,Cd);
+                        {{isValidMiscReg(MISCREG_CR(MODRM_REG))}},Rd,Cd);
                     0x1: MOV(Rd,Dd);
                     0x2: CondInst::MOV(
                         {{isValidMiscReg(MISCREG_CR(MODRM_REG))}},Cd,Rd);