Merge more changes in from head.

[gem5.git] / src / arch / x86 / isa / includes.isa

diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 65e735b0396df3434af5ff7d8ecfbe5efdbb0f61..58aef7b1ded787da555d06e5a5a8a0c00326bbc3 100644 (file)
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -83,24 +83,36 @@
 
 ////////////////////////////////////////////////////////////////////
 //
-// Output include file directives.
+// Output include file directives. Also import the python modules we
+// need for all the x86 custom decoder stuff
 //
 
+let {{
+    import copy
+}};
+
 output header {{
 #include <cstring>
 #include <sstream>
 #include <iostream>
 
-#include "arch/x86/faults.hh"
+#include "arch/x86/emulenv.hh"
+#include "arch/x86/insts/microldstop.hh"
+#include "arch/x86/insts/microregop.hh"
+#include "arch/x86/insts/static_inst.hh"
 #include "arch/x86/isa_traits.hh"
 #include "arch/x86/regfile.hh"
+#include "arch/x86/types.hh"
 #include "base/misc.hh"
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"
-#include "mem/request.hh"  // some constructors use MemReq flags
+#include "sim/faults.hh"
 }};
 
 output decoder {{
+#include "arch/x86/faults.hh"
+#include "arch/x86/miscregs.hh"
+#include "arch/x86/segmentregs.hh"
 #include "base/cprintf.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/thread_context.hh"  // for Jump::branchTarget()