misc: Merge branch v20.1.0.3 hotfix into develop

[gem5.git] / src / arch / x86 / isa / microops / specop.isa

diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa
index 5c242e2c962e4f4a402959732255fa1302ec2840..aad171a56c9dd18bdfdcb842fb134d9193d4e4c6 100644 (file)
--- a/src/arch/x86/isa/microops/specop.isa
+++ b/src/arch/x86/isa/microops/specop.isa
@@ -33,8 +33,6 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Gabe Black
 
 //////////////////////////////////////////////////////////////////////////
 //
@@ -54,7 +52,7 @@ output header {{
                 uint64_t setFlags, Fault _fault, uint8_t _cc);
 
         std::string generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const;
+                const Loader::SymbolTable *symtab) const override;
     };
 
     class MicroHalt : public X86ISA::X86MicroopBase
@@ -63,31 +61,35 @@ output header {{
         MicroHalt(ExtMachInst _machInst, const char * instMnem,
                 uint64_t setFlags) :
             X86MicroopBase(_machInst, "halt", instMnem,
-                           setFlags | (ULL(1) << StaticInst::IsNonSpeculative),
+                           setFlags | (ULL(1) << StaticInst::IsNonSpeculative) |
+                           (ULL(1) << StaticInst::IsQuiesce),
                            No_OpClass)
         {
         }
 
-        %(BasicExecDeclare)s
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const;
+                const Loader::SymbolTable *symtab) const override;
     };
 }};
 
 def template MicroFaultDeclare {{
     class %(class_name)s : public %(base_class)s
     {
+      private:
+        %(reg_idx_arr_decl)s;
+
       public:
         %(class_name)s(ExtMachInst _machInst, const char * instMnem,
                 uint64_t setFlags, Fault _fault, uint8_t _cc);
 
-        %(BasicExecDeclare)s
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
 def template MicroFaultExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+        Fault %(class_name)s::execute(ExecContext *xc,
                 Trace::InstRecord *traceData) const
         {
             %(op_decl)s;
@@ -103,8 +105,7 @@ def template MicroFaultExecute {{
 
 output exec {{
     Fault
-    MicroHalt::execute(%(CPU_exec_context)s *xc,
-            Trace::InstRecord * traceData) const
+    MicroHalt::execute(ExecContext *xc, Trace::InstRecord * traceData) const
     {
         xc->tcBase()->suspend();
         return NoFault;
@@ -112,7 +113,7 @@ output exec {{
 }};
 
 output decoder {{
-    inline MicroFaultBase::MicroFaultBase(
+    MicroFaultBase::MicroFaultBase(
             ExtMachInst machInst, const char * instMnem,
             uint64_t setFlags, Fault _fault, uint8_t _cc) :
         X86MicroopBase(machInst, "fault", instMnem, setFlags, No_OpClass),
@@ -122,18 +123,20 @@ output decoder {{
 }};
 
 def template MicroFaultConstructor {{
-    inline %(class_name)s::%(class_name)s(
+    %(class_name)s::%(class_name)s(
             ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
             Fault _fault, uint8_t _cc) :
         %(base_class)s(machInst, instMnem, setFlags, _fault, _cc)
     {
+        %(set_reg_idx_arr)s;
         %(constructor)s;
     }
 }};
 
 output decoder {{
-    std::string MicroFaultBase::generateDisassembly(Addr pc,
-            const SymbolTable *symtab) const
+    std::string
+    MicroFaultBase::generateDisassembly(
+            Addr pc, const Loader::SymbolTable *symtab) const
     {
         std::stringstream response;
 
@@ -146,8 +149,9 @@ output decoder {{
         return response.str();
     }
 
-    std::string MicroHalt::generateDisassembly(Addr pc,
-            const SymbolTable *symtab) const
+    std::string
+    MicroHalt::generateDisassembly(
+            Addr pc, const Loader::SymbolTable *symtab) const
     {
         std::stringstream response;
 
@@ -164,7 +168,7 @@ let {{
             self.fault = fault
             if flags:
                 if not isinstance(flags, (list, tuple)):
-                    raise Exception, "flags must be a list or tuple of flags"
+                    raise Exception("flags must be a list or tuple of flags")
                 self.cond = " | ".join(flags)
                 self.className += "Flags"
             else:
@@ -181,7 +185,8 @@ let {{
 
     iop = InstObjParams("fault", "MicroFaultFlags", "MicroFaultBase",
             {"code": "",
-             "cond_test": "checkCondition(ccFlagBits, cc)"})
+             "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
+                                          ecfBit | ezfBit, cc)"})
     exec_output = MicroFaultExecute.subst(iop)
     header_output = MicroFaultDeclare.subst(iop)
     decoder_output = MicroFaultConstructor.subst(iop)
@@ -208,21 +213,25 @@ let {{
 def template MicroFenceOpDeclare {{
     class %(class_name)s : public X86ISA::X86MicroopBase
     {
+      private:
+        %(reg_idx_arr_decl)s;
+
       public:
         %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
                 uint64_t setFlags);
 
-        %(BasicExecDeclare)s
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
 def template MicroFenceOpConstructor {{
-    inline %(class_name)s::%(class_name)s(
+    %(class_name)s::%(class_name)s(
             ExtMachInst machInst, const char * instMnem, uint64_t setFlags) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                 setFlags, %(op_class)s)
     {
+        %(set_reg_idx_arr)s;
         %(constructor)s;
     }
 }};
@@ -232,7 +241,8 @@ let {{
         def __init__(self):
             self.className = "Mfence"
             self.mnemonic = "mfence"
-            self.instFlags = "| (1ULL << StaticInst::IsMemBarrier)"
+            self.instFlags = "| (1ULL << StaticInst::IsReadBarrier)" + \
+                             "| (1ULL << StaticInst::IsWriteBarrier)"
 
         def getAllocator(self, microFlags):
             allocString = '''