arch,cpu: Add a setThreadContext method to the ISA class.

[gem5.git] / src / arch / x86 / isa.hh

diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 285f0aa82f3793f072a798e123d9be6d3bc27a7b..855c8e7b3095120eddbcc6ebd5ab29d6eff0a7f1 100644 (file)
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -24,53 +24,90 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
  */
 
 #ifndef __ARCH_X86_ISA_HH__
 #define __ARCH_X86_ISA_HH__
 
-#include "arch/x86/miscregs.hh"
+#include <iostream>
+#include <string>
+
+#include "arch/generic/isa.hh"
 #include "arch/x86/registers.hh"
+#include "arch/x86/regs/float.hh"
+#include "arch/x86/regs/misc.hh"
 #include "base/types.hh"
-
-#include <string>
-#include <iostream>
+#include "cpu/reg_class.hh"
+#include "sim/sim_object.hh"
 
 class Checkpoint;
 class EventManager;
 class ThreadContext;
+struct X86ISAParams;
 
 namespace X86ISA
 {
-    class ISA
+    class ISA : public BaseISA
     {
       protected:
-        MiscReg regVal[NUM_MISCREGS];
+        RegVal regVal[NUM_MISCREGS];
         void updateHandyM5Reg(Efer efer, CR0 cr0,
                 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
 
       public:
         void clear();
 
-        ISA()
+        typedef X86ISAParams Params;
+
+        ISA(Params *p);
+        const Params *params() const;
+
+        RegVal readMiscRegNoEffect(int miscReg) const;
+        RegVal readMiscReg(int miscReg);
+
+        void setMiscRegNoEffect(int miscReg, RegVal val);
+        void setMiscReg(int miscReg, RegVal val);
+
+        RegId
+        flattenRegId(const RegId& regId) const
         {
-            clear();
+            switch (regId.classValue()) {
+              case IntRegClass:
+                return RegId(IntRegClass, flattenIntIndex(regId.index()));
+              case FloatRegClass:
+                return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+              case CCRegClass:
+                return RegId(CCRegClass, flattenCCIndex(regId.index()));
+              case MiscRegClass:
+                return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+              default:
+                break;
+            }
+            return regId;
         }
 
-        MiscReg readMiscRegNoEffect(int miscReg);
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+        int flattenIntIndex(int reg) const { return reg & ~IntFoldBit; }
+
+        int
+        flattenFloatIndex(int reg) const
+        {
+            if (reg >= NUM_FLOATREGS) {
+                reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
+                                     regVal[MISCREG_X87_TOP]);
+            }
+            return reg;
+        }
 
-        void setMiscRegNoEffect(int miscReg, MiscReg val);
-        void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
+        int flattenVecIndex(int reg) const { return reg; }
+        int flattenVecElemIndex(int reg) const { return reg; }
+        int flattenVecPredIndex(int reg) const { return reg; }
+        int flattenCCIndex(int reg) const { return reg; }
+        int flattenMiscIndex(int reg) const { return reg; }
 
-        int flattenIntIndex(int reg);
-        int flattenFloatIndex(int reg);
+        void serialize(CheckpointOut &cp) const override;
+        void unserialize(CheckpointIn &cp) override;
 
-        void serialize(EventManager *em, std::ostream &os);
-        void unserialize(EventManager *em, Checkpoint *cp,
-                const std::string &section);
+        void setThreadContext(ThreadContext *_tc) override;
     };
 }