#ifndef __ARCH_X86_ISA_HH__
#define __ARCH_X86_ISA_HH__
-#include "arch/x86/miscregfile.hh"
-#include "arch/x86/types.hh"
+#include <iostream>
+#include <string>
+
+#include "arch/x86/regs/float.hh"
+#include "arch/x86/regs/misc.hh"
+#include "arch/x86/registers.hh"
+#include "base/types.hh"
+#include "cpu/reg_class.hh"
+#include "sim/sim_object.hh"
class Checkpoint;
class EventManager;
+class ThreadContext;
+struct X86ISAParams;
namespace X86ISA
{
- class ISA
+ class ISA : public SimObject
{
protected:
- MiscRegFile miscRegFile;
+ RegVal regVal[NUM_MISCREGS];
+ void updateHandyM5Reg(Efer efer, CR0 cr0,
+ SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
+ ThreadContext *tc);
public:
- int instAsid()
+ typedef X86ISAParams Params;
+
+ void clear();
+
+ ISA(Params *p);
+ const Params *params() const;
+
+ RegVal readMiscRegNoEffect(int miscReg) const;
+ RegVal readMiscReg(int miscReg, ThreadContext *tc);
+
+ void setMiscRegNoEffect(int miscReg, RegVal val);
+ void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
+
+ RegId
+ flattenRegId(const RegId& regId) const
{
- //XXX This doesn't make sense in x86
- return 0;
+ switch (regId.classValue()) {
+ case IntRegClass:
+ return RegId(IntRegClass, flattenIntIndex(regId.index()));
+ case FloatRegClass:
+ return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+ case CCRegClass:
+ return RegId(CCRegClass, flattenCCIndex(regId.index()));
+ case MiscRegClass:
+ return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+ default:
+ break;
+ }
+ return regId;
}
- int dataAsid()
+ int
+ flattenIntIndex(int reg) const
{
- //XXX This doesn't make sense in x86
- return 0;
+ return reg & ~IntFoldBit;
}
- void clear();
+ int
+ flattenFloatIndex(int reg) const
+ {
+ if (reg >= NUM_FLOATREGS) {
+ reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
+ regVal[MISCREG_X87_TOP]);
+ }
+ return reg;
+ }
- MiscReg readMiscRegNoEffect(int miscReg);
- MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+ int
+ flattenVecIndex(int reg) const
+ {
+ return reg;
+ }
- void setMiscRegNoEffect(int miscReg, const MiscReg val);
- void setMiscReg(int miscReg, const MiscReg val,
- ThreadContext *tc);
+ int
+ flattenVecElemIndex(int reg) const
+ {
+ return reg;
+ }
+
+ int
+ flattenVecPredIndex(int reg) const
+ {
+ return reg;
+ }
+
+ int
+ flattenCCIndex(int reg) const
+ {
+ return reg;
+ }
+
+ int
+ flattenMiscIndex(int reg) const
+ {
+ return reg;
+ }
+
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
+
+ void startup(ThreadContext *tc);
- int flattenIntIndex(int reg);
- int flattenFloatIndex(int reg);
+ /// Explicitly import the otherwise hidden startup
+ using SimObject::startup;
- void serialize(EventManager *em, std::ostream &os);
- void unserialize(EventManager *em, Checkpoint *cp,
- const std::string §ion);
};
}