mem-cache: Add multiple eviction stats

[gem5.git] / src / arch / x86 / isa.hh

diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 8d3b110c6e98c3d330149f7e5360f009d3bfb419..a835a794a5b21ae94cfb72b2751d997e8f6dc456 100644 (file)
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -31,49 +31,71 @@
 #ifndef __ARCH_X86_ISA_HH__
 #define __ARCH_X86_ISA_HH__
 
-#include "arch/x86/floatregs.hh"
-#include "arch/x86/miscregs.hh"
+#include <iostream>
+#include <string>
+
+#include "arch/x86/regs/float.hh"
+#include "arch/x86/regs/misc.hh"
 #include "arch/x86/registers.hh"
 #include "base/types.hh"
-
-#include <string>
-#include <iostream>
+#include "cpu/reg_class.hh"
+#include "sim/sim_object.hh"
 
 class Checkpoint;
 class EventManager;
 class ThreadContext;
+struct X86ISAParams;
 
 namespace X86ISA
 {
-    class ISA
+    class ISA : public SimObject
     {
       protected:
-        MiscReg regVal[NUM_MISCREGS];
+        RegVal regVal[NUM_MISCREGS];
         void updateHandyM5Reg(Efer efer, CR0 cr0,
-                SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
+                SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
+                ThreadContext *tc);
 
       public:
+        typedef X86ISAParams Params;
+
         void clear();
 
-        ISA()
-        {
-            clear();
-        }
+        ISA(Params *p);
+        const Params *params() const;
 
-        MiscReg readMiscRegNoEffect(int miscReg);
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+        RegVal readMiscRegNoEffect(int miscReg) const;
+        RegVal readMiscReg(int miscReg, ThreadContext *tc);
 
-        void setMiscRegNoEffect(int miscReg, MiscReg val);
-        void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
+        void setMiscRegNoEffect(int miscReg, RegVal val);
+        void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
+
+        RegId
+        flattenRegId(const RegId& regId) const
+        {
+            switch (regId.classValue()) {
+              case IntRegClass:
+                return RegId(IntRegClass, flattenIntIndex(regId.index()));
+              case FloatRegClass:
+                return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+              case CCRegClass:
+                return RegId(CCRegClass, flattenCCIndex(regId.index()));
+              case MiscRegClass:
+                return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+              default:
+                break;
+            }
+            return regId;
+        }
 
         int
-        flattenIntIndex(int reg)
+        flattenIntIndex(int reg) const
         {
-            return reg & ~(1 << 6);
+            return reg & ~IntFoldBit;
         }
 
         int
-        flattenFloatIndex(int reg)
+        flattenFloatIndex(int reg) const
         {
             if (reg >= NUM_FLOATREGS) {
                 reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
@@ -82,9 +104,44 @@ namespace X86ISA
             return reg;
         }
 
-        void serialize(EventManager *em, std::ostream &os);
-        void unserialize(EventManager *em, Checkpoint *cp,
-                const std::string &section);
+        int
+        flattenVecIndex(int reg) const
+        {
+            return reg;
+        }
+
+        int
+        flattenVecElemIndex(int reg) const
+        {
+            return reg;
+        }
+
+        int
+        flattenVecPredIndex(int reg) const
+        {
+            return reg;
+        }
+
+        int
+        flattenCCIndex(int reg) const
+        {
+            return reg;
+        }
+
+        int
+        flattenMiscIndex(int reg) const
+        {
+            return reg;
+        }
+
+        void serialize(CheckpointOut &cp) const override;
+        void unserialize(CheckpointIn &cp) override;
+
+        void startup(ThreadContext *tc);
+
+        /// Explicitly import the otherwise hidden startup
+        using SimObject::startup;
+
     };
 }