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#ifndef __ARCH_X86_ISATRAITS_HH__
#define __ARCH_X86_ISATRAITS_HH__
-#include "arch/x86/intregs.hh"
#include "arch/x86/types.hh"
#include "arch/x86/x86_traits.hh"
-
-class StaticInstPtr;
+#include "base/compiler.hh"
+#include "base/types.hh"
namespace LittleEndianGuest {}
//are used.
using namespace LittleEndianGuest;
- // X86 does not have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
- // X86 NOP (XCHG rAX, rAX)
- //XXX This needs to be set to an intermediate instruction struct
- //which encodes this instruction
-
- // These enumerate all the registers for dependence tracking.
- enum DependenceTags {
- //There are 16 microcode registers at the moment. This is an
- //unusually large constant to make sure there isn't overflow.
- FP_Base_DepTag = 128,
- Ctrl_Base_DepTag =
- FP_Base_DepTag +
- //mmx/x87 registers
- 8 +
- //xmm registers
- 16
- };
-
- // semantically meaningful register indices
- //There is no such register in X86
- const int ZeroReg = NUM_INTREGS;
- const int StackPointerReg = INTREG_RSP;
- //X86 doesn't seem to have a link register
- const int ReturnAddressReg = 0;
- const int ReturnValueReg = INTREG_RAX;
- const int FramePointerReg = INTREG_RBP;
- const int ArgumentReg[] = {
- INTREG_RDI,
- INTREG_RSI,
- INTREG_RDX,
- //This argument register is r10 for syscalls and rcx for C.
- INTREG_R10W,
- //INTREG_RCX,
- INTREG_R8W,
- INTREG_R9W
- };
- const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
-
- // Some OS syscalls use a second register (rdx) to return a second
- // value
- const int SyscallPseudoReturnReg = INTREG_RDX;
-
- //XXX These numbers are bogus
- const int MaxInstSrcRegs = 10;
- const int MaxInstDestRegs = 10;
-
- //4k. This value is not constant on x86.
- const int LogVMPageSize = 12;
- const int VMPageSize = (1 << LogVMPageSize);
-
- const int PageShift = 13;
- const int PageBytes = 1ULL << PageShift;
+ const Addr PageShift = 12;
+ const Addr PageBytes = ULL(1) << PageShift;
- const int BranchPredAddrShiftAmt = 0;
+ // Memory accesses can be unaligned
+ const bool HasUnalignedMemAcc = true;
- StaticInstPtr decodeInst(ExtMachInst);
-};
+ const bool CurThreadInfoImplemented = false;
+ const int CurThreadInfoReg = -1;
+}
#endif // __ARCH_X86_ISATRAITS_HH__