#include "arch/x86/miscregfile.hh"
#include "arch/x86/tlb.hh"
+#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "sim/serialize.hh"
memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
}
-MiscReg MiscRegFile::readRegNoEffect(int miscReg)
+MiscReg MiscRegFile::readRegNoEffect(MiscRegIndex miscReg)
{
// Make sure we're not dealing with an illegal control register.
// Instructions should filter out these indexes, and nothing else should
return regVal[miscReg];
}
-MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
+MiscReg MiscRegFile::readReg(MiscRegIndex miscReg, ThreadContext * tc)
{
- if (miscReg >= MISCREG_APIC_START && miscReg <= MISCREG_APIC_END) {
- if (miscReg >= MISCREG_APIC_IN_SERVICE(0) &&
- miscReg <= MISCREG_APIC_IN_SERVICE(15)) {
- panic("Local APIC In-Service registers are unimplemented.\n");
- }
- if (miscReg >= MISCREG_APIC_TRIGGER_MODE(0) &&
- miscReg <= MISCREG_APIC_TRIGGER_MODE(15)) {
- panic("Local APIC Trigger Mode registers are unimplemented.\n");
- }
- if (miscReg >= MISCREG_APIC_INTERRUPT_REQUEST(0) &&
- miscReg <= MISCREG_APIC_INTERRUPT_REQUEST(15)) {
- panic("Local APIC Interrupt Request registers "
- "are unimplemented.\n");
- }
- switch (miscReg) {
- case MISCREG_APIC_TASK_PRIORITY:
- panic("Local APIC Task Priority register unimplemented.\n");
- break;
- case MISCREG_APIC_ARBITRATION_PRIORITY:
- panic("Local APIC Arbitration Priority register unimplemented.\n");
- break;
- case MISCREG_APIC_PROCESSOR_PRIORITY:
- panic("Local APIC Processor Priority register unimplemented.\n");
- break;
- case MISCREG_APIC_EOI:
- panic("Local APIC EOI register unimplemented.\n");
- break;
- case MISCREG_APIC_LOGICAL_DESTINATION:
- panic("Local APIC Logical Destination register unimplemented.\n");
- break;
- case MISCREG_APIC_DESTINATION_FORMAT:
- panic("Local APIC Destination Format register unimplemented.\n");
- break;
- case MISCREG_APIC_ERROR_STATUS:
- regVal[MISCREG_APIC_INTERNAL_STATE] &= ~ULL(0x1);
- break;
- case MISCREG_APIC_INTERRUPT_COMMAND_LOW:
- panic("Local APIC Interrupt Command low"
- " register unimplemented.\n");
- break;
- case MISCREG_APIC_INTERRUPT_COMMAND_HIGH:
- panic("Local APIC Interrupt Command high"
- " register unimplemented.\n");
- break;
- case MISCREG_APIC_INITIAL_COUNT:
- panic("Local APIC Initial Count register unimplemented.\n");
- break;
- case MISCREG_APIC_CURRENT_COUNT:
- panic("Local APIC Current Count register unimplemented.\n");
- break;
- case MISCREG_APIC_DIVIDE_COUNT:
- panic("Local APIC Divide Count register unimplemented.\n");
- break;
- }
+ if (miscReg == MISCREG_TSC) {
+ return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
}
return readRegNoEffect(miscReg);
}
-void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
+void MiscRegFile::setRegNoEffect(MiscRegIndex miscReg, const MiscReg &val)
{
// Make sure we're not dealing with an illegal control register.
// Instructions should filter out these indexes, and nothing else should
regVal[miscReg] = val;
}
-void MiscRegFile::setReg(int miscReg,
+void MiscRegFile::setReg(MiscRegIndex miscReg,
const MiscReg &val, ThreadContext * tc)
{
MiscReg newVal = val;
- if (miscReg >= MISCREG_APIC_START && miscReg <= MISCREG_APIC_END) {
- if (miscReg >= MISCREG_APIC_IN_SERVICE(0) &&
- miscReg <= MISCREG_APIC_IN_SERVICE(15)) {
- panic("Local APIC In-Service registers are unimplemented.\n");
- }
- if (miscReg >= MISCREG_APIC_TRIGGER_MODE(0) &&
- miscReg <= MISCREG_APIC_TRIGGER_MODE(15)) {
- panic("Local APIC Trigger Mode registers are unimplemented.\n");
- }
- if (miscReg >= MISCREG_APIC_INTERRUPT_REQUEST(0) &&
- miscReg <= MISCREG_APIC_INTERRUPT_REQUEST(15)) {
- panic("Local APIC Interrupt Request registers "
- "are unimplemented.\n");
- }
- switch (miscReg) {
- case MISCREG_APIC_ID:
- panic("Local APIC ID register unimplemented.\n");
- break;
- case MISCREG_APIC_VERSION:
- panic("Local APIC Version register is read only.\n");
- break;
- case MISCREG_APIC_TASK_PRIORITY:
- panic("Local APIC Task Priority register unimplemented.\n");
- break;
- case MISCREG_APIC_ARBITRATION_PRIORITY:
- panic("Local APIC Arbitration Priority register unimplemented.\n");
- break;
- case MISCREG_APIC_PROCESSOR_PRIORITY:
- panic("Local APIC Processor Priority register unimplemented.\n");
- break;
- case MISCREG_APIC_EOI:
- panic("Local APIC EOI register unimplemented.\n");
- break;
- case MISCREG_APIC_LOGICAL_DESTINATION:
- panic("Local APIC Logical Destination register unimplemented.\n");
- break;
- case MISCREG_APIC_DESTINATION_FORMAT:
- panic("Local APIC Destination Format register unimplemented.\n");
- break;
- case MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR:
- regVal[MISCREG_APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
- regVal[MISCREG_APIC_INTERNAL_STATE] |= val & (1 << 8);
- if (val & (1 << 9))
- warn("Focus processor checking not implemented.\n");
- break;
- case MISCREG_APIC_ERROR_STATUS:
- {
- if (regVal[MISCREG_APIC_INTERNAL_STATE] & 0x1) {
- regVal[MISCREG_APIC_INTERNAL_STATE] &= ~ULL(0x1);
- newVal = 0;
- } else {
- regVal[MISCREG_APIC_INTERNAL_STATE] |= ULL(0x1);
- return;
- }
-
- }
- break;
- case MISCREG_APIC_INTERRUPT_COMMAND_LOW:
- panic("Local APIC Interrupt Command low"
- " register unimplemented.\n");
- break;
- case MISCREG_APIC_INTERRUPT_COMMAND_HIGH:
- panic("Local APIC Interrupt Command high"
- " register unimplemented.\n");
- break;
- case MISCREG_APIC_LVT_TIMER:
- case MISCREG_APIC_LVT_THERMAL_SENSOR:
- case MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
- case MISCREG_APIC_LVT_LINT0:
- case MISCREG_APIC_LVT_LINT1:
- case MISCREG_APIC_LVT_ERROR:
- {
- uint64_t readOnlyMask = (1 << 12) | (1 << 14);
- newVal = (val & ~readOnlyMask) |
- (regVal[miscReg] & readOnlyMask);
- }
- break;
- case MISCREG_APIC_INITIAL_COUNT:
- panic("Local APIC Initial Count register unimplemented.\n");
- break;
- case MISCREG_APIC_CURRENT_COUNT:
- panic("Local APIC Current Count register unimplemented.\n");
- break;
- case MISCREG_APIC_DIVIDE_COUNT:
- panic("Local APIC Divide Count register unimplemented.\n");
- break;
- }
- setRegNoEffect(miscReg, newVal);
- return;
- }
switch(miscReg)
{
case MISCREG_CR0:
CR0 toggled = regVal[miscReg] ^ val;
CR0 newCR0 = val;
Efer efer = regVal[MISCREG_EFER];
+ HandyM5Reg m5reg = regVal[MISCREG_M5_REG];
if (toggled.pg && efer.lme) {
if (newCR0.pg) {
//Turning on long mode
efer.lma = 1;
+ m5reg.mode = LongMode;
regVal[MISCREG_EFER] = efer;
} else {
//Turning off long mode
efer.lma = 0;
+ m5reg.mode = LegacyMode;
regVal[MISCREG_EFER] = efer;
}
}
+ // Figure out what submode we're in.
+ if (m5reg.mode == LongMode) {
+ SegAttr csAttr = regVal[MISCREG_CS_ATTR];
+ if (csAttr.longMode)
+ m5reg.submode = SixtyFourBitMode;
+ else
+ m5reg.submode = CompatabilityMode;
+ } else {
+ if (newCR0.pe) {
+ RFLAGS rflags = regVal[MISCREG_RFLAGS];
+ if (rflags.vm)
+ m5reg.submode = Virtual8086Mode;
+ else
+ m5reg.submode = ProtectedMode;
+ } else {
+ m5reg.submode = RealMode;
+ }
+ }
+ regVal[MISCREG_M5_REG] = m5reg;
if (toggled.pg) {
tc->getITBPtr()->invalidateAll();
tc->getDTBPtr()->invalidateAll();
{
SegAttr toggled = regVal[miscReg] ^ val;
SegAttr newCSAttr = val;
+ HandyM5Reg m5reg = regVal[MISCREG_M5_REG];
if (toggled.longMode) {
- SegAttr newCSAttr = val;
if (newCSAttr.longMode) {
+ if (m5reg.mode == LongMode)
+ m5reg.submode = SixtyFourBitMode;
regVal[MISCREG_ES_EFF_BASE] = 0;
regVal[MISCREG_CS_EFF_BASE] = 0;
regVal[MISCREG_SS_EFF_BASE] = 0;
regVal[MISCREG_DS_EFF_BASE] = 0;
} else {
+ if (m5reg.mode == LongMode)
+ m5reg.submode = CompatabilityMode;
regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE];
regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE];
regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
}
}
+ m5reg.cpl = newCSAttr.dpl;
+ regVal[MISCREG_M5_REG] = m5reg;
}
break;
// These segments always actually use their bases, or in other words
MISCREG_SEG_BASE_BASE)] = val;
}
break;
+ case MISCREG_TSC:
+ regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
+ return;
+ default:
+ break;
}
setRegNoEffect(miscReg, newVal);
}
projects / gem5.git / blobdiff