/*
- * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use of this software in source and binary forms,
#ifndef __ARCH_X86_MISCREGS_HH__
#define __ARCH_X86_MISCREGS_HH__
+#include "arch/x86/segmentregs.hh"
#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
OFBit = 1 << 11
};
+ enum RFLAGBit {
+ TFBit = 1 << 8,
+ IFBit = 1 << 9,
+ NTBit = 1 << 14,
+ RFBit = 1 << 16,
+ VMBit = 1 << 17,
+ ACBit = 1 << 18,
+ VIFBit = 1 << 19,
+ VIPBit = 1 << 20,
+ IDBit = 1 << 21
+ };
+
enum MiscRegIndex
{
// Control registers
// Flags register
MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
+ //Register to keep handy values like the CPU mode in.
+ MISCREG_M5_REG,
+
/*
* Model Specific Registers
*/
MISCREG_MTRR_PHYS_BASE_5,
MISCREG_MTRR_PHYS_BASE_6,
MISCREG_MTRR_PHYS_BASE_7,
+ MISCREG_MTRR_PHYS_BASE_END,
- MISCREG_MTRR_PHYS_MASK_BASE,
+ MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END,
MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
MISCREG_MTRR_PHYS_MASK_1,
MISCREG_MTRR_PHYS_MASK_2,
MISCREG_MTRR_PHYS_MASK_5,
MISCREG_MTRR_PHYS_MASK_6,
MISCREG_MTRR_PHYS_MASK_7,
+ MISCREG_MTRR_PHYS_MASK_END,
- MISCREG_MTRR_FIX_64K_00000,
+ MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END,
MISCREG_MTRR_FIX_16K_80000,
MISCREG_MTRR_FIX_16K_A0000,
MISCREG_MTRR_FIX_4K_C0000,
MISCREG_MC2_CTL,
MISCREG_MC3_CTL,
MISCREG_MC4_CTL,
+ MISCREG_MC5_CTL,
+ MISCREG_MC6_CTL,
+ MISCREG_MC7_CTL,
+ MISCREG_MC_CTL_END,
- MISCREG_MC_STATUS_BASE,
+ MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END,
MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
MISCREG_MC1_STATUS,
MISCREG_MC2_STATUS,
MISCREG_MC3_STATUS,
MISCREG_MC4_STATUS,
+ MISCREG_MC5_STATUS,
+ MISCREG_MC6_STATUS,
+ MISCREG_MC7_STATUS,
+ MISCREG_MC_STATUS_END,
- MISCREG_MC_ADDR_BASE,
+ MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END,
MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
MISCREG_MC1_ADDR,
MISCREG_MC2_ADDR,
MISCREG_MC3_ADDR,
MISCREG_MC4_ADDR,
+ MISCREG_MC5_ADDR,
+ MISCREG_MC6_ADDR,
+ MISCREG_MC7_ADDR,
+ MISCREG_MC_ADDR_END,
- MISCREG_MC_MISC_BASE,
+ MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END,
MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
MISCREG_MC1_MISC,
MISCREG_MC2_MISC,
MISCREG_MC3_MISC,
MISCREG_MC4_MISC,
+ MISCREG_MC5_MISC,
+ MISCREG_MC6_MISC,
+ MISCREG_MC7_MISC,
+ MISCREG_MC_MISC_END,
// Extended feature enable register
- MISCREG_EFER,
+ MISCREG_EFER = MISCREG_MC_MISC_END,
MISCREG_STAR,
MISCREG_LSTAR,
MISCREG_PERF_EVT_SEL1,
MISCREG_PERF_EVT_SEL2,
MISCREG_PERF_EVT_SEL3,
+ MISCREG_PERF_EVT_SEL_END,
- MISCREG_PERF_EVT_CTR_BASE,
+ MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END,
MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
MISCREG_PERF_EVT_CTR1,
MISCREG_PERF_EVT_CTR2,
MISCREG_PERF_EVT_CTR3,
+ MISCREG_PERF_EVT_CTR_END,
- MISCREG_SYSCFG,
+ MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END,
MISCREG_IORR_BASE_BASE,
MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
MISCREG_IORR_BASE1,
+ MISCREG_IORR_BASE_END,
- MISCREG_IORR_MASK_BASE,
+ MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END,
MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
MISCREG_IORR_MASK1,
+ MISCREG_IORR_MASK_END,
- MISCREG_TOP_MEM,
+ MISCREG_TOP_MEM = MISCREG_IORR_MASK_END,
MISCREG_TOP_MEM2,
MISCREG_VM_CR,
MISCREG_DS,
MISCREG_FS,
MISCREG_GS,
+ MISCREG_HS,
+ MISCREG_TSL,
+ MISCREG_TSG,
+ MISCREG_LS,
+ MISCREG_MS,
+ MISCREG_TR,
+ MISCREG_IDTR,
// Hidden segment base field
- MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments,
+ MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
MISCREG_CS_BASE,
MISCREG_SS_BASE,
MISCREG_DS_BASE,
MISCREG_FS_BASE,
MISCREG_GS_BASE,
+ MISCREG_HS_BASE,
+ MISCREG_TSL_BASE,
+ MISCREG_TSG_BASE,
+ MISCREG_LS_BASE,
+ MISCREG_MS_BASE,
+ MISCREG_TR_BASE,
+ MISCREG_IDTR_BASE,
+
+ // The effective segment base, ie what is actually added to an
+ // address. In 64 bit mode this can be different from the above,
+ // namely 0.
+ MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
+ MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
+ MISCREG_CS_EFF_BASE,
+ MISCREG_SS_EFF_BASE,
+ MISCREG_DS_EFF_BASE,
+ MISCREG_FS_EFF_BASE,
+ MISCREG_GS_EFF_BASE,
+ MISCREG_HS_EFF_BASE,
+ MISCREG_TSL_EFF_BASE,
+ MISCREG_TSG_EFF_BASE,
+ MISCREG_LS_EFF_BASE,
+ MISCREG_MS_EFF_BASE,
+ MISCREG_TR_EFF_BASE,
+ MISCREG_IDTR_EFF_BASE,
// Hidden segment limit field
- MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
+ MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
MISCREG_CS_LIMIT,
MISCREG_SS_LIMIT,
MISCREG_DS_LIMIT,
MISCREG_FS_LIMIT,
MISCREG_GS_LIMIT,
+ MISCREG_HS_LIMIT,
+ MISCREG_TSL_LIMIT,
+ MISCREG_TSG_LIMIT,
+ MISCREG_LS_LIMIT,
+ MISCREG_MS_LIMIT,
+ MISCREG_TR_LIMIT,
+ MISCREG_IDTR_LIMIT,
// Hidden segment limit attributes
- MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments,
+ MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
MISCREG_CS_ATTR,
MISCREG_SS_ATTR,
MISCREG_DS_ATTR,
MISCREG_FS_ATTR,
MISCREG_GS_ATTR,
-
- // System segment selectors
- MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments,
- MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
- MISCREG_TR,
-
- // Hidden system segment base field
- MISCREG_SYSSEG_BASE_BASE = MISCREG_SYSSEG_SEL_BASE + NumSysSegments,
- MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
- MISCREG_TR_BASE,
- MISCREG_GDTR_BASE,
- MISCREG_IDTR_BASE,
-
- // Hidden system segment limit field
- MISCREG_SYSSEG_LIMIT_BASE = MISCREG_SYSSEG_BASE_BASE + NumSysSegments,
- MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
- MISCREG_TR_LIMIT,
- MISCREG_GDTR_LIMIT,
- MISCREG_IDTR_LIMIT,
-
- // Hidden system segment attribute field
- MISCREG_SYSSEG_ATTR_BASE = MISCREG_SYSSEG_LIMIT_BASE + NumSysSegments,
- MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
+ MISCREG_HS_ATTR,
+ MISCREG_TSL_ATTR,
+ MISCREG_TSG_ATTR,
+ MISCREG_LS_ATTR,
+ MISCREG_MS_ATTR,
MISCREG_TR_ATTR,
+ MISCREG_IDTR_ATTR,
// Floating point control registers
- MISCREG_X87_TOP = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments,
+ MISCREG_X87_TOP =
+ MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
+
+ MISCREG_MXCSR,
+ MISCREG_FCW,
+ MISCREG_FSW,
+ MISCREG_FTW,
+ MISCREG_FTAG,
+ MISCREG_FISEG,
+ MISCREG_FIOFF,
+ MISCREG_FOSEG,
+ MISCREG_FOOFF,
+ MISCREG_FOP,
//XXX Add "Model-Specific Registers"
+ MISCREG_APIC_BASE,
+
+ // "Fake" MSRs for internally implemented devices
+ MISCREG_PCI_CONFIG_ADDRESS,
+
NUM_MISCREGS
};
static inline MiscRegIndex
MISCREG_CR(int index)
{
+ assert(index >= 0 && index < NumCRegs);
return (MiscRegIndex)(MISCREG_CR_BASE + index);
}
static inline MiscRegIndex
MISCREG_DR(int index)
{
+ assert(index >= 0 && index < NumDRegs);
return (MiscRegIndex)(MISCREG_DR_BASE + index);
}
static inline MiscRegIndex
MISCREG_MTRR_PHYS_BASE(int index)
{
+ assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END -
+ MISCREG_MTRR_PHYS_BASE_BASE));
return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
}
static inline MiscRegIndex
MISCREG_MTRR_PHYS_MASK(int index)
{
+ assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END -
+ MISCREG_MTRR_PHYS_MASK_BASE));
return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
}
static inline MiscRegIndex
MISCREG_MC_CTL(int index)
{
+ assert(index >= 0 && index < (MISCREG_MC_CTL_END -
+ MISCREG_MC_CTL_BASE));
return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
}
static inline MiscRegIndex
MISCREG_MC_STATUS(int index)
{
+ assert(index >= 0 && index < (MISCREG_MC_STATUS_END -
+ MISCREG_MC_STATUS_BASE));
return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
}
static inline MiscRegIndex
MISCREG_MC_ADDR(int index)
{
+ assert(index >= 0 && index < (MISCREG_MC_ADDR_END -
+ MISCREG_MC_ADDR_BASE));
return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
}
static inline MiscRegIndex
MISCREG_MC_MISC(int index)
{
+ assert(index >= 0 && index < (MISCREG_MC_MISC_END -
+ MISCREG_MC_MISC_BASE));
return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
}
static inline MiscRegIndex
MISCREG_PERF_EVT_SEL(int index)
{
+ assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END -
+ MISCREG_PERF_EVT_SEL_BASE));
return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
}
static inline MiscRegIndex
MISCREG_PERF_EVT_CTR(int index)
{
+ assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END -
+ MISCREG_PERF_EVT_CTR_BASE));
return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
}
static inline MiscRegIndex
MISCREG_IORR_BASE(int index)
{
+ assert(index >= 0 && index < (MISCREG_IORR_BASE_END -
+ MISCREG_IORR_BASE_BASE));
return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
}
static inline MiscRegIndex
MISCREG_IORR_MASK(int index)
{
+ assert(index >= 0 && index < (MISCREG_IORR_MASK_END -
+ MISCREG_IORR_MASK_BASE));
return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
}
static inline MiscRegIndex
MISCREG_SEG_SEL(int index)
{
+ assert(index >= 0 && index < NUM_SEGMENTREGS);
return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
}
static inline MiscRegIndex
MISCREG_SEG_BASE(int index)
{
+ assert(index >= 0 && index < NUM_SEGMENTREGS);
return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
}
static inline MiscRegIndex
- MISCREG_SEG_LIMIT(int index)
- {
- return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
- }
-
- static inline MiscRegIndex
- MISCREG_SEG_ATTR(int index)
- {
- return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
- }
-
- static inline MiscRegIndex
- MISCREG_SYSSEG_SEL(int index)
+ MISCREG_SEG_EFF_BASE(int index)
{
- return (MiscRegIndex)(MISCREG_SYSSEG_SEL_BASE + index);
+ assert(index >= 0 && index < NUM_SEGMENTREGS);
+ return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
}
static inline MiscRegIndex
- MISCREG_SYSSEG_BASE(int index)
- {
- return (MiscRegIndex)(MISCREG_SYSSEG_BASE_BASE + index);
- }
-
- static inline MiscRegIndex
- MISCREG_SYSSEG_LIMIT(int index)
+ MISCREG_SEG_LIMIT(int index)
{
- return (MiscRegIndex)(MISCREG_SYSSEG_LIMIT_BASE + index);
+ assert(index >= 0 && index < NUM_SEGMENTREGS);
+ return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
}
static inline MiscRegIndex
- MISCREG_SYSSEG_ATTR(int index)
+ MISCREG_SEG_ATTR(int index)
{
- return (MiscRegIndex)(MISCREG_SYSSEG_ATTR_BASE + index);
+ assert(index >= 0 && index < NUM_SEGMENTREGS);
+ return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
}
/**
Bitfield<0> cf; // Carry Flag
EndBitUnion(RFLAGS)
+ BitUnion64(HandyM5Reg)
+ Bitfield<0> mode;
+ Bitfield<3, 1> submode;
+ Bitfield<5, 4> cpl;
+ Bitfield<6> paging;
+ Bitfield<7> prot;
+ Bitfield<9, 8> defOp;
+ Bitfield<11, 10> altOp;
+ Bitfield<13, 12> defAddr;
+ Bitfield<15, 14> altAddr;
+ Bitfield<17, 16> stack;
+ EndBitUnion(HandyM5Reg)
+
/**
* Control registers
*/
Bitfield<3, 0> tpr; // Task Priority Register
EndBitUnion(CR8)
+ BitUnion64(DR6)
+ Bitfield<0> b0;
+ Bitfield<1> b1;
+ Bitfield<2> b2;
+ Bitfield<3> b3;
+ Bitfield<13> bd;
+ Bitfield<14> bs;
+ Bitfield<15> bt;
+ EndBitUnion(DR6)
+
+ BitUnion64(DR7)
+ Bitfield<0> l0;
+ Bitfield<1> g0;
+ Bitfield<2> l1;
+ Bitfield<3> g1;
+ Bitfield<4> l2;
+ Bitfield<5> g2;
+ Bitfield<6> l3;
+ Bitfield<7> g3;
+ Bitfield<8> le;
+ Bitfield<9> ge;
+ Bitfield<13> gd;
+ Bitfield<17, 16> rw0;
+ Bitfield<19, 18> len0;
+ Bitfield<21, 20> rw1;
+ Bitfield<23, 22> len1;
+ Bitfield<25, 24> rw2;
+ Bitfield<27, 26> len2;
+ Bitfield<29, 28> rw3;
+ Bitfield<31, 30> len3;
+ EndBitUnion(DR7)
+
// MTRR capabilities
BitUnion64(MTRRcap)
Bitfield<7, 0> vcnt; // Variable-Range Register Count
* Segment Selector
*/
BitUnion64(SegSelector)
+ // The following bitfield is not defined in the ISA, but it's useful
+ // when checking selectors in larger data types to make sure they
+ // aren't too large.
+ Bitfield<63, 3> esi; // Extended selector
Bitfield<15, 3> si; // Selector Index
Bitfield<2> ti; // Table Indicator
Bitfield<1, 0> rpl; // Requestor Privilege Level
EndBitUnion(SegDescriptor)
BitUnion64(SegAttr)
- Bitfield<0> writable;
- Bitfield<1> readable;
- Bitfield<2> expandDown;
- Bitfield<4, 3> dpl;
- Bitfield<5> defaultSize;
- Bitfield<6> longMode;
+ Bitfield<1, 0> dpl;
+ Bitfield<2> unusable;
+ Bitfield<3> defaultSize;
+ Bitfield<4> longMode;
+ Bitfield<5> avl;
+ Bitfield<6> granularity;
+ Bitfield<7> present;
+ Bitfield<11, 8> type;
+ Bitfield<12> writable;
+ Bitfield<13> readable;
+ Bitfield<14> expandDown;
+ Bitfield<15> system;
EndBitUnion(SegAttr)
BitUnion64(GateDescriptor)
*/
BitUnion64(TR)
EndBitUnion(TR)
+
+
+ /**
+ * Local APIC Base Register
+ */
+ BitUnion64(LocalApicBase)
+ Bitfield<51, 12> base;
+ Bitfield<11> enable;
+ Bitfield<8> bsp;
+ EndBitUnion(LocalApicBase)
};
#endif // __ARCH_X86_INTREGS_HH__
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