MISCREG_MTRR_PHYS_BASE_5,
MISCREG_MTRR_PHYS_BASE_6,
MISCREG_MTRR_PHYS_BASE_7,
+ MISCREG_MTRR_PHYS_BASE_END,
- MISCREG_MTRR_PHYS_MASK_BASE,
+ MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END,
MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
MISCREG_MTRR_PHYS_MASK_1,
MISCREG_MTRR_PHYS_MASK_2,
MISCREG_MTRR_PHYS_MASK_5,
MISCREG_MTRR_PHYS_MASK_6,
MISCREG_MTRR_PHYS_MASK_7,
+ MISCREG_MTRR_PHYS_MASK_END,
- MISCREG_MTRR_FIX_64K_00000,
+ MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END,
MISCREG_MTRR_FIX_16K_80000,
MISCREG_MTRR_FIX_16K_A0000,
MISCREG_MTRR_FIX_4K_C0000,
MISCREG_MC5_CTL,
MISCREG_MC6_CTL,
MISCREG_MC7_CTL,
+ MISCREG_MC_CTL_END,
- MISCREG_MC_STATUS_BASE,
+ MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END,
MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
MISCREG_MC1_STATUS,
MISCREG_MC2_STATUS,
MISCREG_MC5_STATUS,
MISCREG_MC6_STATUS,
MISCREG_MC7_STATUS,
+ MISCREG_MC_STATUS_END,
- MISCREG_MC_ADDR_BASE,
+ MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END,
MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
MISCREG_MC1_ADDR,
MISCREG_MC2_ADDR,
MISCREG_MC5_ADDR,
MISCREG_MC6_ADDR,
MISCREG_MC7_ADDR,
+ MISCREG_MC_ADDR_END,
- MISCREG_MC_MISC_BASE,
+ MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END,
MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
MISCREG_MC1_MISC,
MISCREG_MC2_MISC,
MISCREG_MC5_MISC,
MISCREG_MC6_MISC,
MISCREG_MC7_MISC,
+ MISCREG_MC_MISC_END,
// Extended feature enable register
- MISCREG_EFER,
+ MISCREG_EFER = MISCREG_MC_MISC_END,
MISCREG_STAR,
MISCREG_LSTAR,
MISCREG_PERF_EVT_SEL1,
MISCREG_PERF_EVT_SEL2,
MISCREG_PERF_EVT_SEL3,
+ MISCREG_PERF_EVT_SEL_END,
- MISCREG_PERF_EVT_CTR_BASE,
+ MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END,
MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
MISCREG_PERF_EVT_CTR1,
MISCREG_PERF_EVT_CTR2,
MISCREG_PERF_EVT_CTR3,
+ MISCREG_PERF_EVT_CTR_END,
- MISCREG_SYSCFG,
+ MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END,
MISCREG_IORR_BASE_BASE,
MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
MISCREG_IORR_BASE1,
+ MISCREG_IORR_BASE_END,
- MISCREG_IORR_MASK_BASE,
+ MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END,
MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
MISCREG_IORR_MASK1,
+ MISCREG_IORR_MASK_END,
- MISCREG_TOP_MEM,
+ MISCREG_TOP_MEM = MISCREG_IORR_MASK_END,
MISCREG_TOP_MEM2,
MISCREG_VM_CR,
MISCREG_X87_TOP =
MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
+ MISCREG_MXCSR,
+ MISCREG_FCW,
+ MISCREG_FSW,
+ MISCREG_FTW,
+ MISCREG_FTAG,
+ MISCREG_FISEG,
+ MISCREG_FIOFF,
+ MISCREG_FOSEG,
+ MISCREG_FOOFF,
+ MISCREG_FOP,
+
//XXX Add "Model-Specific Registers"
MISCREG_APIC_BASE,
static inline MiscRegIndex
MISCREG_CR(int index)
{
+ assert(index >= 0 && index < NumCRegs);
return (MiscRegIndex)(MISCREG_CR_BASE + index);
}
static inline MiscRegIndex
MISCREG_DR(int index)
{
+ assert(index >= 0 && index < NumDRegs);
return (MiscRegIndex)(MISCREG_DR_BASE + index);
}
static inline MiscRegIndex
MISCREG_MTRR_PHYS_BASE(int index)
{
+ assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END -
+ MISCREG_MTRR_PHYS_BASE_BASE));
return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
}
static inline MiscRegIndex
MISCREG_MTRR_PHYS_MASK(int index)
{
+ assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END -
+ MISCREG_MTRR_PHYS_MASK_BASE));
return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
}
static inline MiscRegIndex
MISCREG_MC_CTL(int index)
{
+ assert(index >= 0 && index < (MISCREG_MC_CTL_END -
+ MISCREG_MC_CTL_BASE));
return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
}
static inline MiscRegIndex
MISCREG_MC_STATUS(int index)
{
+ assert(index >= 0 && index < (MISCREG_MC_STATUS_END -
+ MISCREG_MC_STATUS_BASE));
return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
}
static inline MiscRegIndex
MISCREG_MC_ADDR(int index)
{
+ assert(index >= 0 && index < (MISCREG_MC_ADDR_END -
+ MISCREG_MC_ADDR_BASE));
return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
}
static inline MiscRegIndex
MISCREG_MC_MISC(int index)
{
+ assert(index >= 0 && index < (MISCREG_MC_MISC_END -
+ MISCREG_MC_MISC_BASE));
return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
}
static inline MiscRegIndex
MISCREG_PERF_EVT_SEL(int index)
{
+ assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END -
+ MISCREG_PERF_EVT_SEL_BASE));
return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
}
static inline MiscRegIndex
MISCREG_PERF_EVT_CTR(int index)
{
+ assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END -
+ MISCREG_PERF_EVT_CTR_BASE));
return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
}
static inline MiscRegIndex
MISCREG_IORR_BASE(int index)
{
+ assert(index >= 0 && index < (MISCREG_IORR_BASE_END -
+ MISCREG_IORR_BASE_BASE));
return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
}
static inline MiscRegIndex
MISCREG_IORR_MASK(int index)
{
+ assert(index >= 0 && index < (MISCREG_IORR_MASK_END -
+ MISCREG_IORR_MASK_BASE));
return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
}
static inline MiscRegIndex
MISCREG_SEG_SEL(int index)
{
+ assert(index >= 0 && index < NUM_SEGMENTREGS);
return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
}
static inline MiscRegIndex
MISCREG_SEG_BASE(int index)
{
+ assert(index >= 0 && index < NUM_SEGMENTREGS);
return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
}
static inline MiscRegIndex
MISCREG_SEG_EFF_BASE(int index)
{
+ assert(index >= 0 && index < NUM_SEGMENTREGS);
return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
}
static inline MiscRegIndex
MISCREG_SEG_LIMIT(int index)
{
+ assert(index >= 0 && index < NUM_SEGMENTREGS);
return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
}
static inline MiscRegIndex
MISCREG_SEG_ATTR(int index)
{
+ assert(index >= 0 && index < NUM_SEGMENTREGS);
return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
}
Bitfield<0> mode;
Bitfield<3, 1> submode;
Bitfield<5, 4> cpl;
+ Bitfield<6> paging;
+ Bitfield<7> prot;
+ Bitfield<9, 8> defOp;
+ Bitfield<11, 10> altOp;
+ Bitfield<13, 12> defAddr;
+ Bitfield<15, 14> altAddr;
+ Bitfield<17, 16> stack;
EndBitUnion(HandyM5Reg)
/**
Bitfield<3, 0> tpr; // Task Priority Register
EndBitUnion(CR8)
+ BitUnion64(DR6)
+ Bitfield<0> b0;
+ Bitfield<1> b1;
+ Bitfield<2> b2;
+ Bitfield<3> b3;
+ Bitfield<13> bd;
+ Bitfield<14> bs;
+ Bitfield<15> bt;
+ EndBitUnion(DR6)
+
+ BitUnion64(DR7)
+ Bitfield<0> l0;
+ Bitfield<1> g0;
+ Bitfield<2> l1;
+ Bitfield<3> g1;
+ Bitfield<4> l2;
+ Bitfield<5> g2;
+ Bitfield<6> l3;
+ Bitfield<7> g3;
+ Bitfield<8> le;
+ Bitfield<9> ge;
+ Bitfield<13> gd;
+ Bitfield<17, 16> rw0;
+ Bitfield<19, 18> len0;
+ Bitfield<21, 20> rw1;
+ Bitfield<23, 22> len1;
+ Bitfield<25, 24> rw2;
+ Bitfield<27, 26> len2;
+ Bitfield<29, 28> rw3;
+ Bitfield<31, 30> len3;
+ EndBitUnion(DR7)
+
// MTRR capabilities
BitUnion64(MTRRcap)
Bitfield<7, 0> vcnt; // Variable-Range Register Count
EndBitUnion(SegDescriptor)
BitUnion64(SegAttr)
- Bitfield<0> writable;
- Bitfield<1> readable;
- Bitfield<2> expandDown;
- Bitfield<4, 3> dpl;
- Bitfield<5> defaultSize;
- Bitfield<6> longMode;
+ Bitfield<1, 0> dpl;
+ Bitfield<2> unusable;
+ Bitfield<3> defaultSize;
+ Bitfield<4> longMode;
+ Bitfield<5> avl;
+ Bitfield<6> granularity;
+ Bitfield<7> present;
+ Bitfield<11, 8> type;
+ Bitfield<12> writable;
+ Bitfield<13> readable;
+ Bitfield<14> expandDown;
+ Bitfield<15> system;
EndBitUnion(SegAttr)
BitUnion64(GateDescriptor)
projects / gem5.git / blobdiff