arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / x86 / nativetrace.cc

diff --git a/src/arch/x86/nativetrace.cc b/src/arch/x86/nativetrace.cc
index d8b3564a39e2be82f34034c2d9f3d9e6888fb1f2..142a51cd76299c45b9f59aa917774d930fe9341e 100644 (file)
--- a/src/arch/x86/nativetrace.cc
+++ b/src/arch/x86/nativetrace.cc
@@ -28,10 +28,11 @@
  * Authors: Gabe Black
  */
 
+#include "arch/x86/nativetrace.hh"
+
+#include "arch/x86/isa_traits.hh"
 #include "arch/x86/regs/float.hh"
 #include "arch/x86/regs/int.hh"
-#include "arch/x86/isa_traits.hh"
-#include "arch/x86/nativetrace.hh"
 #include "cpu/thread_context.hh"
 #include "debug/ExecRegDelta.hh"
 #include "params/X86NativeTrace.hh"
@@ -89,9 +90,9 @@ X86NativeTrace::ThreadState::update(ThreadContext *tc)
     rip = tc->pcState().npc();
     //This should be expanded if x87 registers are considered
     for (int i = 0; i < 8; i++)
-        mmx[i] = tc->readFloatRegBits(X86ISA::FLOATREG_MMX(i));
+        mmx[i] = tc->readFloatReg(X86ISA::FLOATREG_MMX(i));
     for (int i = 0; i < 32; i++)
-        xmm[i] = tc->readFloatRegBits(X86ISA::FLOATREG_XMM_BASE + i);
+        xmm[i] = tc->readFloatReg(X86ISA::FLOATREG_XMM_BASE + i);
 }