X86: Compute PCI config addresses correctly.

[gem5.git] / src / arch / x86 / pagetable.hh

diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh
index 8ca179c86c0475c99b8f0ba051187ae48d230d59..e42693c03d9d6a3c137b267d1bcf7be19786e0da 100644 (file)
--- a/src/arch/x86/pagetable.hh
+++ b/src/arch/x86/pagetable.hh
@@ -58,18 +58,68 @@
 #ifndef __ARCH_X86_PAGETABLE_HH__
 #define __ARCH_X86_PAGETABLE_HH__
 
+#include <iostream>
+#include <string>
+
 #include "sim/host.hh"
+#include "base/bitunion.hh"
 #include "base/misc.hh"
 
+class Checkpoint;
+
 namespace X86ISA
 {
-    struct VAddr
-    {
-        VAddr(Addr a) { panic("not implemented yet."); }
-    };
+    BitUnion64(VAddr)
+        Bitfield<20, 12> longl1;
+        Bitfield<29, 21> longl2;
+        Bitfield<38, 30> longl3;
+        Bitfield<47, 39> longl4;
+
+        Bitfield<20, 12> pael1;
+        Bitfield<29, 21> pael2;
+        Bitfield<31, 30> pael3;
+
+        Bitfield<21, 12> norml1;
+        Bitfield<31, 22> norml2;
+    EndBitUnion(VAddr)
 
-    class PageTableEntry
+    struct TlbEntry
     {
+        // The base of the physical page.
+        Addr paddr;
+
+        // The beginning of the virtual page this entry maps.
+        Addr vaddr;
+        // The size of the page this entry represents.
+        Addr size;
+
+        // Read permission is always available, assuming it isn't blocked by
+        // other mechanisms.
+        bool writable;
+        // Whether this page is accesible without being in supervisor mode.
+        bool user;
+        // Whether to use write through or write back. M5 ignores this and
+        // lets the caches handle the writeback policy.
+        //bool pwt;
+        // Whether the page is cacheable or not.
+        bool uncacheable;
+        // Whether or not to kick this page out on a write to CR3.
+        bool global;
+        // A bit used to form an index into the PAT table.
+        bool patBit;
+        // Whether or not memory on this page can be executed.
+        bool noExec;
+
+        TlbEntry(Addr asn, Addr _vaddr, Addr _paddr);
+        TlbEntry() {}
+
+        Addr pageStart()
+        {
+            return paddr;
+        }
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
     };
 }