mem-cache: Add multiple eviction stats

[gem5.git] / src / arch / x86 / pagetable.hh

diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh
index 8a6e71f3b44aea8ffb69828642c745f94cd21125..f5e1a05f00cf61e4baa6112243ae5454ec1b2bbd 100644 (file)
--- a/src/arch/x86/pagetable.hh
+++ b/src/arch/x86/pagetable.hh
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
  * Copyright (c) 2007 The Hewlett-Packard Development Company
  * All rights reserved.
  *
@@ -42,13 +43,16 @@
 
 #include <iostream>
 #include <string>
+#include <vector>
 
 #include "base/bitunion.hh"
-#include "base/misc.hh"
 #include "base/types.hh"
 #include "base/trie.hh"
+#include "arch/x86/system.hh"
+#include "debug/MMU.hh"
 
 class Checkpoint;
+class ThreadContext;
 
 namespace X86ISA
 {
@@ -59,21 +63,7 @@ typedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie;
 
 namespace X86ISA
 {
-    BitUnion64(VAddr)
-        Bitfield<20, 12> longl1;
-        Bitfield<29, 21> longl2;
-        Bitfield<38, 30> longl3;
-        Bitfield<47, 39> longl4;
-
-        Bitfield<20, 12> pael1;
-        Bitfield<29, 21> pael2;
-        Bitfield<31, 30> pael3;
-
-        Bitfield<21, 12> norml1;
-        Bitfield<31, 22> norml2;
-    EndBitUnion(VAddr)
-
-    struct TlbEntry
+    struct TlbEntry : public Serializable
     {
         // The base of the physical page.
         Addr paddr;
@@ -104,8 +94,9 @@ namespace X86ISA
 
         TlbEntryTrie::Handle trieHandle;
 
-        TlbEntry(Addr asn, Addr _vaddr, Addr _paddr);
-        TlbEntry() {}
+        TlbEntry(Addr asn, Addr _vaddr, Addr _paddr,
+                 bool uncacheable, bool read_only);
+        TlbEntry();
 
         void
         updateVaddr(Addr new_vaddr)
@@ -118,8 +109,96 @@ namespace X86ISA
             return paddr;
         }
 
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
+        // Return the page size in bytes
+        int size()
+        {
+            return (1 << logBytes);
+        }
+
+        void serialize(CheckpointOut &cp) const override;
+        void unserialize(CheckpointIn &cp) override;
+    };
+
+
+    BitUnion64(VAddr)
+        Bitfield<20, 12> longl1;
+        Bitfield<29, 21> longl2;
+        Bitfield<38, 30> longl3;
+        Bitfield<47, 39> longl4;
+
+        Bitfield<20, 12> pael1;
+        Bitfield<29, 21> pael2;
+        Bitfield<31, 30> pael3;
+
+        Bitfield<21, 12> norml1;
+        Bitfield<31, 22> norml2;
+    EndBitUnion(VAddr)
+
+    // Unfortunately, the placement of the base field in a page table entry is
+    // very erratic and would make a mess here. It might be moved here at some
+    // point in the future.
+    BitUnion64(PageTableEntry)
+        Bitfield<63> nx;
+        Bitfield<51, 12> base;
+        Bitfield<11, 9> avl;
+        Bitfield<8> g;
+        Bitfield<7> ps;
+        Bitfield<6> d;
+        Bitfield<5> a;
+        Bitfield<4> pcd;
+        Bitfield<3> pwt;
+        Bitfield<2> u;
+        Bitfield<1> w;
+        Bitfield<0> p;
+    EndBitUnion(PageTableEntry)
+
+    template <int first, int last>
+    class LongModePTE
+    {
+      public:
+        Addr paddr() { return pte.base << PageShift; }
+        void paddr(Addr addr) { pte.base = addr >> PageShift; }
+
+        bool present() { return pte.p; }
+        void present(bool p) { pte.p = p ? 1 : 0; }
+
+        bool uncacheable() { return pte.pcd; }
+        void uncacheable(bool u) { pte.pcd = u ? 1 : 0; }
+
+        bool readonly() { return !pte.w; }
+        void readonly(bool r) { pte.w = r ? 0 : 1; }
+
+        void
+        read(PortProxy &p, Addr table, Addr vaddr)
+        {
+            entryAddr = table;
+            entryAddr += bits(vaddr, first, last) * sizeof(PageTableEntry);
+            pte = p.read<PageTableEntry>(entryAddr);
+        }
+
+        void
+        reset(Addr _paddr, bool _present=true,
+              bool _uncacheable=false, bool _readonly=false)
+        {
+            pte = 0;
+            pte.u = 1;
+            paddr(_paddr);
+            present(_present);
+            uncacheable(_uncacheable);
+            readonly(_readonly);
+        };
+
+        void write(PortProxy &p) { p.write(entryAddr, pte); }
+
+        static int
+        tableSize()
+        {
+            return 1 << ((first - last) + 4 - PageShift);
+        }
+
+      protected:
+        PageTableEntry pte;
+        Addr entryAddr;
     };
 }