MEM: Introduce the master/slave port sub-classes in C++

[gem5.git] / src / arch / x86 / pagetable_walker.hh

diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh
index 90f07528060df3ff8bd03f322c75c42142c6d371..bf7a9e6150d8a06628ff459ba8594be38490fb9b 100644 (file)
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -60,11 +60,11 @@ namespace X86ISA
     {
       protected:
         // Port for accessing memory
-        class WalkerPort : public Port
+        class WalkerPort : public MasterPort
         {
           public:
             WalkerPort(const std::string &_name, Walker * _walker) :
-                  Port(_name, _walker), walker(_walker)
+                  MasterPort(_name, _walker), walker(_walker)
             {}
 
           protected:
@@ -73,9 +73,8 @@ namespace X86ISA
             bool recvTiming(PacketPtr pkt);
             Tick recvAtomic(PacketPtr pkt);
             void recvFunctional(PacketPtr pkt);
-            void recvRangeChange();
             void recvRetry();
-            bool isSnooping() { return true; }
+            bool isSnooping() const { return true; }
         };
 
         friend class WalkerPort;
@@ -166,7 +165,7 @@ namespace X86ISA
                 RequestPtr req, BaseTLB::Mode mode);
         Fault startFunctional(ThreadContext * _tc, Addr &addr,
                 Addr &pageSize, BaseTLB::Mode mode);
-        Port *getPort(const std::string &if_name, int idx = -1);
+        MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
 
       protected:
         // The TLB we're supposed to load.