/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
+ * Copyright (c) 2018 TU Dresden
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
+ * Maximilian Stein
*/
+#include "arch/x86/system.hh"
+
#include "arch/x86/bios/intelmp.hh"
#include "arch/x86/bios/smbios.hh"
-#include "arch/x86/regs/misc.hh"
#include "arch/x86/isa_traits.hh"
-#include "arch/x86/system.hh"
-#include "arch/vtophys.hh"
#include "base/loader/object_file.hh"
-#include "base/loader/symtab.hh"
-#include "base/intmath.hh"
-#include "base/trace.hh"
#include "cpu/thread_context.hh"
-#include "mem/port_proxy.hh"
#include "params/X86System.hh"
-#include "sim/byteswap.hh"
-using namespace LittleEndianGuest;
using namespace X86ISA;
X86System::X86System(Params *p) :
X86ISA::installSegDesc(ThreadContext *tc, SegmentRegIndex seg,
SegDescriptor desc, bool longmode)
{
- uint64_t base = desc.baseLow + (desc.baseHigh << 24);
bool honorBase = !longmode || seg == SEGMENT_REG_FS ||
seg == SEGMENT_REG_GS ||
seg == SEGMENT_REG_TSL ||
seg == SYS_SEGMENT_REG_TR;
- uint64_t limit = desc.limitLow | (desc.limitHigh << 16);
SegAttr attr = 0;
attr.expandDown = 0;
}
- tc->setMiscReg(MISCREG_SEG_BASE(seg), base);
- tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? base : 0);
- tc->setMiscReg(MISCREG_SEG_LIMIT(seg), limit);
- tc->setMiscReg(MISCREG_SEG_ATTR(seg), (MiscReg)attr);
+ tc->setMiscReg(MISCREG_SEG_BASE(seg), desc.base);
+ tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? desc.base : 0);
+ tc->setMiscReg(MISCREG_SEG_LIMIT(seg), desc.limit);
+ tc->setMiscReg(MISCREG_SEG_ATTR(seg), (RegVal)attr);
}
void
uint8_t numGDTEntries = 0;
// Place holder at selector 0
uint64_t nullDescriptor = 0;
- physProxy.writeBlob(GDTBase + numGDTEntries * 8,
- (uint8_t *)(&nullDescriptor), 8);
+ physProxy.writeBlob(GDTBase + numGDTEntries * 8, &nullDescriptor, 8);
numGDTEntries++;
SegDescriptor initDesc = 0;
initDesc.d = 0; // operand size
initDesc.g = 1; // granularity
initDesc.s = 1; // system segment
- initDesc.limitHigh = 0xFFFF;
- initDesc.limitLow = 0xF;
- initDesc.baseHigh = 0x0;
- initDesc.baseLow = 0x0;
+ initDesc.limit = 0xFFFFFFFF;
+ initDesc.base = 0;
- //64 bit code segment
+ // 64 bit code segment
SegDescriptor csDesc = initDesc;
csDesc.type.codeOrData = 1;
csDesc.dpl = 0;
- //Because we're dealing with a pointer and I don't think it's
- //guaranteed that there isn't anything in a nonvirtual class between
- //it's beginning in memory and it's actual data, we'll use an
- //intermediary.
+ // Because we're dealing with a pointer and I don't think it's
+ // guaranteed that there isn't anything in a nonvirtual class between
+ // it's beginning in memory and it's actual data, we'll use an
+ // intermediary.
uint64_t csDescVal = csDesc;
- physProxy.writeBlob(GDTBase + numGDTEntries * 8,
- (uint8_t *)(&csDescVal), 8);
+ physProxy.writeBlob(GDTBase + numGDTEntries * 8, (&csDescVal), 8);
numGDTEntries++;
SegSelector cs = 0;
cs.si = numGDTEntries - 1;
- tc->setMiscReg(MISCREG_CS, (MiscReg)cs);
+ tc->setMiscReg(MISCREG_CS, (RegVal)cs);
- //32 bit data segment
+ // 32 bit data segment
SegDescriptor dsDesc = initDesc;
uint64_t dsDescVal = dsDesc;
- physProxy.writeBlob(GDTBase + numGDTEntries * 8,
- (uint8_t *)(&dsDescVal), 8);
+ physProxy.writeBlob(GDTBase + numGDTEntries * 8, (&dsDescVal), 8);
numGDTEntries++;
SegSelector ds = 0;
ds.si = numGDTEntries - 1;
- tc->setMiscReg(MISCREG_DS, (MiscReg)ds);
- tc->setMiscReg(MISCREG_ES, (MiscReg)ds);
- tc->setMiscReg(MISCREG_FS, (MiscReg)ds);
- tc->setMiscReg(MISCREG_GS, (MiscReg)ds);
- tc->setMiscReg(MISCREG_SS, (MiscReg)ds);
+ tc->setMiscReg(MISCREG_DS, (RegVal)ds);
+ tc->setMiscReg(MISCREG_ES, (RegVal)ds);
+ tc->setMiscReg(MISCREG_FS, (RegVal)ds);
+ tc->setMiscReg(MISCREG_GS, (RegVal)ds);
+ tc->setMiscReg(MISCREG_SS, (RegVal)ds);
tc->setMiscReg(MISCREG_TSL, 0);
tc->setMiscReg(MISCREG_TSG_BASE, GDTBase);
SegDescriptor tssDesc = initDesc;
uint64_t tssDescVal = tssDesc;
- physProxy.writeBlob(GDTBase + numGDTEntries * 8,
- (uint8_t *)(&tssDescVal), 8);
+ physProxy.writeBlob(GDTBase + numGDTEntries * 8, (&tssDescVal), 8);
numGDTEntries++;
SegSelector tss = 0;
tss.si = numGDTEntries - 1;
- tc->setMiscReg(MISCREG_TR, (MiscReg)tss);
+ tc->setMiscReg(MISCREG_TR, (RegVal)tss);
installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true);
/*
// Page Map Level 4
// read/write, user, not present
- uint64_t pml4e = X86ISA::htog(0x6);
+ uint64_t pml4e = htole<uint64_t>(0x6);
for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) {
- physProxy.writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8);
+ physProxy.writeBlob(PageMapLevel4 + offset, (&pml4e), 8);
}
// Point to the only PDPT
- pml4e = X86ISA::htog(0x7 | PageDirPtrTable);
- physProxy.writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8);
+ pml4e = htole<uint64_t>(0x7 | PageDirPtrTable);
+ physProxy.writeBlob(PageMapLevel4, (&pml4e), 8);
// Page Directory Pointer Table
// read/write, user, not present
- uint64_t pdpe = X86ISA::htog(0x6);
- for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) {
- physProxy.writeBlob(PageDirPtrTable + offset,
- (uint8_t *)(&pdpe), 8);
- }
+ uint64_t pdpe = htole<uint64_t>(0x6);
+ for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8)
+ physProxy.writeBlob(PageDirPtrTable + offset, &pdpe, 8);
// Point to the PDTs
for (int table = 0; table < NumPDTs; table++) {
- pdpe = X86ISA::htog(0x7 | PageDirTable[table]);
- physProxy.writeBlob(PageDirPtrTable + table * 8,
- (uint8_t *)(&pdpe), 8);
+ pdpe = htole<uint64_t>(0x7 | PageDirTable[table]);
+ physProxy.writeBlob(PageDirPtrTable + table * 8, &pdpe, 8);
}
// Page Directory Tables
for (int table = 0; table < NumPDTs; table++) {
for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
// read/write, user, present, 4MB
- uint64_t pdte = X86ISA::htog(0x87 | base);
- physProxy.writeBlob(PageDirTable[table] + offset,
- (uint8_t *)(&pdte), 8);
+ uint64_t pdte = htole(0x87 | base);
+ physProxy.writeBlob(PageDirTable[table] + offset, &pdte, 8);
base += pageSize;
}
}
* Transition from real mode all the way up to Long mode
*/
CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
- //Turn off paging.
+ // Turn off paging.
cr0.pg = 0;
tc->setMiscReg(MISCREG_CR0, cr0);
- //Turn on protected mode.
+ // Turn on protected mode.
cr0.pe = 1;
tc->setMiscReg(MISCREG_CR0, cr0);
CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
- //Turn on pae.
+ // Turn on pae.
cr4.pae = 1;
tc->setMiscReg(MISCREG_CR4, cr4);
- //Point to the page tables.
+ // Point to the page tables.
tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
- //Enable long mode.
+ // Enable long mode.
efer.lme = 1;
tc->setMiscReg(MISCREG_EFER, efer);
- //Start using longmode segments.
+ // Start using longmode segments.
installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
- //Activate long mode.
+ // Activate long mode.
cr0.pg = 1;
tc->setMiscReg(MISCREG_CR0, cr0);
Addr ebdaPos = 0xF0000;
Addr fixed, table;
- //Write out the SMBios/DMI table
+ // Write out the SMBios/DMI table.
writeOutSMBiosTable(ebdaPos, fixed, table);
ebdaPos += (fixed + table);
ebdaPos = roundUp(ebdaPos, 16);
- //Write out the Intel MP Specification configuration table
+ // Write out the Intel MP Specification configuration table.
writeOutMPTable(ebdaPos, fixed, table);
ebdaPos += (fixed + table);
}
Addr &headerSize, Addr &structSize, Addr table)
{
// If the table location isn't specified, just put it after the header.
- // The header size as of the 2.5 SMBios specification is 0x1F bytes
+ // The header size as of the 2.5 SMBios specification is 0x1F bytes.
if (!table)
table = header + 0x1F;
smbiosTable->setTableAddr(table);
projects / gem5.git / blobdiff