*/
#include <cstring>
+#include <memory>
-#include "config/full_system.hh"
-
-#include "arch/x86/faults.hh"
+#include "arch/generic/mmapped_ipr.hh"
#include "arch/x86/insts/microldstop.hh"
-#include "arch/x86/pagetable.hh"
#include "arch/x86/regs/misc.hh"
+#include "arch/x86/regs/msr.hh"
+#include "arch/x86/faults.hh"
+#include "arch/x86/pagetable.hh"
+#include "arch/x86/pagetable_walker.hh"
#include "arch/x86/tlb.hh"
#include "arch/x86/x86_traits.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
-#include "config/full_system.hh"
-#include "cpu/thread_context.hh"
#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
+#include "debug/TLB.hh"
#include "mem/packet_access.hh"
-#include "mem/request.hh"
-
-#if FULL_SYSTEM
-#include "arch/x86/pagetable_walker.hh"
-#else
#include "mem/page_table.hh"
+#include "mem/request.hh"
+#include "sim/full_system.hh"
#include "sim/process.hh"
-#endif
namespace X86ISA {
-TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
+TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size),
+ lruSeq(0)
{
+ if (!size)
+ fatal("TLBs must have a non-zero size.\n");
tlb = new TlbEntry[size];
std::memset(tlb, 0, sizeof(TlbEntry) * size);
- for (int x = 0; x < size; x++)
+ for (int x = 0; x < size; x++) {
+ tlb[x].trieHandle = NULL;
freeList.push_back(&tlb[x]);
+ }
-#if FULL_SYSTEM
walker = p->walker;
walker->setTLB(this);
-#endif
}
-TlbEntry *
-TLB::insert(Addr vpn, TlbEntry &entry)
+void
+TLB::evictLRU()
{
- //TODO Deal with conflicting entries
+ // Find the entry with the lowest (and hence least recently updated)
+ // sequence number.
- TlbEntry *newEntry = NULL;
- if (!freeList.empty()) {
- newEntry = freeList.front();
- freeList.pop_front();
- } else {
- newEntry = entryList.back();
- entryList.pop_back();
+ unsigned lru = 0;
+ for (unsigned i = 1; i < size; i++) {
+ if (tlb[i].lruSeq < tlb[lru].lruSeq)
+ lru = i;
}
- *newEntry = entry;
- newEntry->vaddr = vpn;
- entryList.push_front(newEntry);
- return newEntry;
+
+ assert(tlb[lru].trieHandle);
+ trie.remove(tlb[lru].trieHandle);
+ tlb[lru].trieHandle = NULL;
+ freeList.push_back(&tlb[lru]);
}
-TLB::EntryList::iterator
-TLB::lookupIt(Addr va, bool update_lru)
+TlbEntry *
+TLB::insert(Addr vpn, TlbEntry &entry)
{
- //TODO make this smarter at some point
- EntryList::iterator entry;
- for (entry = entryList.begin(); entry != entryList.end(); entry++) {
- if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
- DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
- "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
- if (update_lru) {
- entryList.push_front(*entry);
- entryList.erase(entry);
- entry = entryList.begin();
- }
- break;
- }
+ // If somebody beat us to it, just use that existing entry.
+ TlbEntry *newEntry = trie.lookup(vpn);
+ if (newEntry) {
+ assert(newEntry->vaddr == vpn);
+ return newEntry;
}
- return entry;
+
+ if (freeList.empty())
+ evictLRU();
+
+ newEntry = freeList.front();
+ freeList.pop_front();
+
+ *newEntry = entry;
+ newEntry->lruSeq = nextSeq();
+ newEntry->vaddr = vpn;
+ newEntry->trieHandle =
+ trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
+ return newEntry;
}
TlbEntry *
TLB::lookup(Addr va, bool update_lru)
{
- EntryList::iterator entry = lookupIt(va, update_lru);
- if (entry == entryList.end())
- return NULL;
- else
- return *entry;
+ TlbEntry *entry = trie.lookup(va);
+ if (entry && update_lru)
+ entry->lruSeq = nextSeq();
+ return entry;
}
void
-TLB::invalidateAll()
+TLB::flushAll()
{
DPRINTF(TLB, "Invalidating all entries.\n");
- while (!entryList.empty()) {
- TlbEntry *entry = entryList.front();
- entryList.pop_front();
- freeList.push_back(entry);
+ for (unsigned i = 0; i < size; i++) {
+ if (tlb[i].trieHandle) {
+ trie.remove(tlb[i].trieHandle);
+ tlb[i].trieHandle = NULL;
+ freeList.push_back(&tlb[i]);
+ }
}
}
}
void
-TLB::invalidateNonGlobal()
+TLB::flushNonGlobal()
{
DPRINTF(TLB, "Invalidating all non global entries.\n");
- EntryList::iterator entryIt;
- for (entryIt = entryList.begin(); entryIt != entryList.end();) {
- if (!(*entryIt)->global) {
- freeList.push_back(*entryIt);
- entryList.erase(entryIt++);
- } else {
- entryIt++;
+ for (unsigned i = 0; i < size; i++) {
+ if (tlb[i].trieHandle && !tlb[i].global) {
+ trie.remove(tlb[i].trieHandle);
+ tlb[i].trieHandle = NULL;
+ freeList.push_back(&tlb[i]);
}
}
}
void
TLB::demapPage(Addr va, uint64_t asn)
{
- EntryList::iterator entry = lookupIt(va, false);
- if (entry != entryList.end()) {
- freeList.push_back(*entry);
- entryList.erase(entry);
+ TlbEntry *entry = trie.lookup(va);
+ if (entry) {
+ trie.remove(entry->trieHandle);
+ entry->trieHandle = NULL;
+ freeList.push_back(entry);
}
}
if (prefix == IntAddrPrefixCPUID) {
panic("CPUID memory space not yet implemented!\n");
} else if (prefix == IntAddrPrefixMSR) {
- vaddr = vaddr >> 3;
- req->setFlags(Request::MMAPED_IPR);
- Addr regNum = 0;
- switch (vaddr & ~IntAddrPrefixMask) {
- case 0x10:
- regNum = MISCREG_TSC;
- break;
- case 0x1B:
- regNum = MISCREG_APIC_BASE;
- break;
- case 0xFE:
- regNum = MISCREG_MTRRCAP;
- break;
- case 0x174:
- regNum = MISCREG_SYSENTER_CS;
- break;
- case 0x175:
- regNum = MISCREG_SYSENTER_ESP;
- break;
- case 0x176:
- regNum = MISCREG_SYSENTER_EIP;
- break;
- case 0x179:
- regNum = MISCREG_MCG_CAP;
- break;
- case 0x17A:
- regNum = MISCREG_MCG_STATUS;
- break;
- case 0x17B:
- regNum = MISCREG_MCG_CTL;
- break;
- case 0x1D9:
- regNum = MISCREG_DEBUG_CTL_MSR;
- break;
- case 0x1DB:
- regNum = MISCREG_LAST_BRANCH_FROM_IP;
- break;
- case 0x1DC:
- regNum = MISCREG_LAST_BRANCH_TO_IP;
- break;
- case 0x1DD:
- regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
- break;
- case 0x1DE:
- regNum = MISCREG_LAST_EXCEPTION_TO_IP;
- break;
- case 0x200:
- regNum = MISCREG_MTRR_PHYS_BASE_0;
- break;
- case 0x201:
- regNum = MISCREG_MTRR_PHYS_MASK_0;
- break;
- case 0x202:
- regNum = MISCREG_MTRR_PHYS_BASE_1;
- break;
- case 0x203:
- regNum = MISCREG_MTRR_PHYS_MASK_1;
- break;
- case 0x204:
- regNum = MISCREG_MTRR_PHYS_BASE_2;
- break;
- case 0x205:
- regNum = MISCREG_MTRR_PHYS_MASK_2;
- break;
- case 0x206:
- regNum = MISCREG_MTRR_PHYS_BASE_3;
- break;
- case 0x207:
- regNum = MISCREG_MTRR_PHYS_MASK_3;
- break;
- case 0x208:
- regNum = MISCREG_MTRR_PHYS_BASE_4;
- break;
- case 0x209:
- regNum = MISCREG_MTRR_PHYS_MASK_4;
- break;
- case 0x20A:
- regNum = MISCREG_MTRR_PHYS_BASE_5;
- break;
- case 0x20B:
- regNum = MISCREG_MTRR_PHYS_MASK_5;
- break;
- case 0x20C:
- regNum = MISCREG_MTRR_PHYS_BASE_6;
- break;
- case 0x20D:
- regNum = MISCREG_MTRR_PHYS_MASK_6;
- break;
- case 0x20E:
- regNum = MISCREG_MTRR_PHYS_BASE_7;
- break;
- case 0x20F:
- regNum = MISCREG_MTRR_PHYS_MASK_7;
- break;
- case 0x250:
- regNum = MISCREG_MTRR_FIX_64K_00000;
- break;
- case 0x258:
- regNum = MISCREG_MTRR_FIX_16K_80000;
- break;
- case 0x259:
- regNum = MISCREG_MTRR_FIX_16K_A0000;
- break;
- case 0x268:
- regNum = MISCREG_MTRR_FIX_4K_C0000;
- break;
- case 0x269:
- regNum = MISCREG_MTRR_FIX_4K_C8000;
- break;
- case 0x26A:
- regNum = MISCREG_MTRR_FIX_4K_D0000;
- break;
- case 0x26B:
- regNum = MISCREG_MTRR_FIX_4K_D8000;
- break;
- case 0x26C:
- regNum = MISCREG_MTRR_FIX_4K_E0000;
- break;
- case 0x26D:
- regNum = MISCREG_MTRR_FIX_4K_E8000;
- break;
- case 0x26E:
- regNum = MISCREG_MTRR_FIX_4K_F0000;
- break;
- case 0x26F:
- regNum = MISCREG_MTRR_FIX_4K_F8000;
- break;
- case 0x277:
- regNum = MISCREG_PAT;
- break;
- case 0x2FF:
- regNum = MISCREG_DEF_TYPE;
- break;
- case 0x400:
- regNum = MISCREG_MC0_CTL;
- break;
- case 0x404:
- regNum = MISCREG_MC1_CTL;
- break;
- case 0x408:
- regNum = MISCREG_MC2_CTL;
- break;
- case 0x40C:
- regNum = MISCREG_MC3_CTL;
- break;
- case 0x410:
- regNum = MISCREG_MC4_CTL;
- break;
- case 0x414:
- regNum = MISCREG_MC5_CTL;
- break;
- case 0x418:
- regNum = MISCREG_MC6_CTL;
- break;
- case 0x41C:
- regNum = MISCREG_MC7_CTL;
- break;
- case 0x401:
- regNum = MISCREG_MC0_STATUS;
- break;
- case 0x405:
- regNum = MISCREG_MC1_STATUS;
- break;
- case 0x409:
- regNum = MISCREG_MC2_STATUS;
- break;
- case 0x40D:
- regNum = MISCREG_MC3_STATUS;
- break;
- case 0x411:
- regNum = MISCREG_MC4_STATUS;
- break;
- case 0x415:
- regNum = MISCREG_MC5_STATUS;
- break;
- case 0x419:
- regNum = MISCREG_MC6_STATUS;
- break;
- case 0x41D:
- regNum = MISCREG_MC7_STATUS;
- break;
- case 0x402:
- regNum = MISCREG_MC0_ADDR;
- break;
- case 0x406:
- regNum = MISCREG_MC1_ADDR;
- break;
- case 0x40A:
- regNum = MISCREG_MC2_ADDR;
- break;
- case 0x40E:
- regNum = MISCREG_MC3_ADDR;
- break;
- case 0x412:
- regNum = MISCREG_MC4_ADDR;
- break;
- case 0x416:
- regNum = MISCREG_MC5_ADDR;
- break;
- case 0x41A:
- regNum = MISCREG_MC6_ADDR;
- break;
- case 0x41E:
- regNum = MISCREG_MC7_ADDR;
- break;
- case 0x403:
- regNum = MISCREG_MC0_MISC;
- break;
- case 0x407:
- regNum = MISCREG_MC1_MISC;
- break;
- case 0x40B:
- regNum = MISCREG_MC2_MISC;
- break;
- case 0x40F:
- regNum = MISCREG_MC3_MISC;
- break;
- case 0x413:
- regNum = MISCREG_MC4_MISC;
- break;
- case 0x417:
- regNum = MISCREG_MC5_MISC;
- break;
- case 0x41B:
- regNum = MISCREG_MC6_MISC;
- break;
- case 0x41F:
- regNum = MISCREG_MC7_MISC;
- break;
- case 0xC0000080:
- regNum = MISCREG_EFER;
- break;
- case 0xC0000081:
- regNum = MISCREG_STAR;
- break;
- case 0xC0000082:
- regNum = MISCREG_LSTAR;
- break;
- case 0xC0000083:
- regNum = MISCREG_CSTAR;
- break;
- case 0xC0000084:
- regNum = MISCREG_SF_MASK;
- break;
- case 0xC0000100:
- regNum = MISCREG_FS_BASE;
- break;
- case 0xC0000101:
- regNum = MISCREG_GS_BASE;
- break;
- case 0xC0000102:
- regNum = MISCREG_KERNEL_GS_BASE;
- break;
- case 0xC0000103:
- regNum = MISCREG_TSC_AUX;
- break;
- case 0xC0010000:
- regNum = MISCREG_PERF_EVT_SEL0;
- break;
- case 0xC0010001:
- regNum = MISCREG_PERF_EVT_SEL1;
- break;
- case 0xC0010002:
- regNum = MISCREG_PERF_EVT_SEL2;
- break;
- case 0xC0010003:
- regNum = MISCREG_PERF_EVT_SEL3;
- break;
- case 0xC0010004:
- regNum = MISCREG_PERF_EVT_CTR0;
- break;
- case 0xC0010005:
- regNum = MISCREG_PERF_EVT_CTR1;
- break;
- case 0xC0010006:
- regNum = MISCREG_PERF_EVT_CTR2;
- break;
- case 0xC0010007:
- regNum = MISCREG_PERF_EVT_CTR3;
- break;
- case 0xC0010010:
- regNum = MISCREG_SYSCFG;
- break;
- case 0xC0010016:
- regNum = MISCREG_IORR_BASE0;
- break;
- case 0xC0010017:
- regNum = MISCREG_IORR_BASE1;
- break;
- case 0xC0010018:
- regNum = MISCREG_IORR_MASK0;
- break;
- case 0xC0010019:
- regNum = MISCREG_IORR_MASK1;
- break;
- case 0xC001001A:
- regNum = MISCREG_TOP_MEM;
- break;
- case 0xC001001D:
- regNum = MISCREG_TOP_MEM2;
- break;
- case 0xC0010114:
- regNum = MISCREG_VM_CR;
- break;
- case 0xC0010115:
- regNum = MISCREG_IGNNE;
- break;
- case 0xC0010116:
- regNum = MISCREG_SMM_CTL;
- break;
- case 0xC0010117:
- regNum = MISCREG_VM_HSAVE_PA;
- break;
- default:
- return new GeneralProtection(0);
- }
+ vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
+ req->setFlags(Request::MMAPPED_IPR);
+
+ MiscRegIndex regNum;
+ if (!msrAddrToIndex(regNum, vaddr))
+ return std::make_shared<GeneralProtection>(0);
+
//The index is multiplied by the size of a MiscReg so that
//any memory dependence calculations will not see these as
//overlapping.
- req->setPaddr(regNum * sizeof(MiscReg));
+ req->setPaddr((Addr)regNum * sizeof(MiscReg));
return NoFault;
} else if (prefix == IntAddrPrefixIO) {
// TODO If CPL > IOPL or in virtual mode, check the I/O permission
// space.
assert(!(IOPort & ~0xFFFF));
if (IOPort == 0xCF8 && req->getSize() == 4) {
- req->setFlags(Request::MMAPED_IPR);
+ req->setFlags(Request::MMAPPED_IPR);
req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
} else if ((IOPort & ~mask(2)) == 0xCFC) {
req->setFlags(Request::UNCACHEABLE);
req->setPaddr(PhysAddrPrefixPciConfig |
mbits(configAddress, 30, 2) |
(IOPort & mask(2)));
+ } else {
+ req->setPaddr(PhysAddrPrefixIO | IOPort);
}
} else {
req->setFlags(Request::UNCACHEABLE);
}
}
+Fault
+TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+{
+ Addr paddr = req->getPaddr();
+
+ AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
+
+ if (m5opRange.contains(paddr)) {
+ if (m5opRange.contains(paddr)) {
+ req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
+ req->setPaddr(GenericISA::iprAddressPseudoInst(
+ (paddr >> 8) & 0xFF,
+ paddr & 0xFF));
+ }
+ } else if (FullSystem) {
+ // Check for an access to the local APIC
+ LocalApicBase localApicBase =
+ tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
+ AddrRange apicRange(localApicBase.base * PageBytes,
+ (localApicBase.base + 1) * PageBytes - 1);
+
+ if (apicRange.contains(paddr)) {
+ // The Intel developer's manuals say the below restrictions apply,
+ // but the linux kernel, because of a compiler optimization, breaks
+ // them.
+ /*
+ // Check alignment
+ if (paddr & ((32/8) - 1))
+ return new GeneralProtection(0);
+ // Check access size
+ if (req->getSize() != (32/8))
+ return new GeneralProtection(0);
+ */
+ // Force the access to be uncacheable.
+ req->setFlags(Request::UNCACHEABLE);
+ req->setPaddr(x86LocalAPICAddress(tc->contextId(),
+ paddr - apicRange.start()));
+ }
+ }
+
+ return NoFault;
+}
+
Fault
TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
Mode mode, bool &delayedResponse, bool timing)
int seg = flags & SegmentFlagMask;
bool storeCheck = flags & (StoreCheck << FlagShift);
+ delayedResponse = false;
+
// If this is true, we're dealing with a request to a non-memory address
// space.
if (seg == SEGMENT_REG_MS) {
return translateInt(req, tc);
}
- delayedResponse = false;
Addr vaddr = req->getVaddr();
DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
&& !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
- return new GeneralProtection(0);
+ return std::make_shared<GeneralProtection>(0);
bool expandDown = false;
SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
if (!attr.writable && (mode == Write || storeCheck))
- return new GeneralProtection(0);
+ return std::make_shared<GeneralProtection>(0);
if (!attr.readable && mode == Read)
- return new GeneralProtection(0);
+ return std::make_shared<GeneralProtection>(0);
expandDown = attr.expandDown;
}
Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
- // This assumes we're not in 64 bit mode. If we were, the default
- // address size is 64 bits, overridable to 32.
- int size = 32;
bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
- SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
- if ((csAttr.defaultSize && sizeOverride) ||
- (!csAttr.defaultSize && !sizeOverride))
- size = 16;
- Addr offset = bits(vaddr - base, size-1, 0);
+ unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr
+ : (unsigned)m5Reg.defAddr;
+ int size = (1 << logSize) * 8;
+ Addr offset = bits(vaddr - base, size - 1, 0);
Addr endOffset = offset + req->getSize() - 1;
if (expandDown) {
DPRINTF(TLB, "Checking an expand down segment.\n");
warn_once("Expand down segments are untested.\n");
if (offset <= limit || endOffset <= limit)
- return new GeneralProtection(0);
+ return std::make_shared<GeneralProtection>(0);
} else {
if (offset > limit || endOffset > limit)
- return new GeneralProtection(0);
+ return std::make_shared<GeneralProtection>(0);
}
}
+ if (m5Reg.submode != SixtyFourBitMode ||
+ (flags & (AddrSizeFlagBit << FlagShift)))
+ vaddr &= mask(32);
// If paging is enabled, do the translation.
if (m5Reg.paging) {
DPRINTF(TLB, "Paging enabled.\n");
// The vaddr already has the segment base applied.
TlbEntry *entry = lookup(vaddr);
if (!entry) {
-#if FULL_SYSTEM
- Fault fault = walker->start(tc, translation, req, mode);
- if (timing || fault != NoFault) {
- // This gets ignored in atomic mode.
- delayedResponse = true;
- return fault;
- }
- entry = lookup(vaddr);
- assert(entry);
-#else
- DPRINTF(TLB, "Handling a TLB miss for "
- "address %#x at pc %#x.\n",
- vaddr, tc->instAddr());
-
- Process *p = tc->getProcessPtr();
- TlbEntry newEntry;
- bool success = p->pTable->lookup(vaddr, newEntry);
- if (!success && mode != Execute) {
- p->checkAndAllocNextPage(vaddr);
- success = p->pTable->lookup(vaddr, newEntry);
- }
- if (!success) {
- return new PageFault(vaddr, true, mode, true, false);
+ if (FullSystem) {
+ Fault fault = walker->start(tc, translation, req, mode);
+ if (timing || fault != NoFault) {
+ // This gets ignored in atomic mode.
+ delayedResponse = true;
+ return fault;
+ }
+ entry = lookup(vaddr);
+ assert(entry);
} else {
- Addr alignedVaddr = p->pTable->pageAlign(vaddr);
- DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
- newEntry.pageStart());
- entry = insert(alignedVaddr, newEntry);
+ DPRINTF(TLB, "Handling a TLB miss for "
+ "address %#x at pc %#x.\n",
+ vaddr, tc->instAddr());
+
+ Process *p = tc->getProcessPtr();
+ TlbEntry newEntry;
+ bool success = p->pTable->lookup(vaddr, newEntry);
+ if (!success && mode != Execute) {
+ // Check if we just need to grow the stack.
+ if (p->fixupStackFault(vaddr)) {
+ // If we did, lookup the entry for the new page.
+ success = p->pTable->lookup(vaddr, newEntry);
+ }
+ }
+ if (!success) {
+ return std::make_shared<PageFault>(vaddr, true, mode,
+ true, false);
+ } else {
+ Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+ DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
+ newEntry.pageStart());
+ entry = insert(alignedVaddr, newEntry);
+ }
+ DPRINTF(TLB, "Miss was serviced.\n");
}
- DPRINTF(TLB, "Miss was serviced.\n");
-#endif
}
+
+ DPRINTF(TLB, "Entry found with paddr %#x, "
+ "doing protection checks.\n", entry->paddr);
// Do paging protection checks.
bool inUser = (m5Reg.cpl == 3 &&
!(flags & (CPL0FlagBit << FlagShift)));
- if ((inUser && !entry->user) ||
- (mode == Write && !entry->writable)) {
+ CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
+ bool badWrite = (!entry->writable && (inUser || cr0.wp));
+ if ((inUser && !entry->user) || (mode == Write && badWrite)) {
// The page must have been present to get into the TLB in
// the first place. We'll assume the reserved bits are
// fine even though we're not checking them.
- return new PageFault(vaddr, true, mode, inUser, false);
+ return std::make_shared<PageFault>(vaddr, true, mode, inUser,
+ false);
}
- if (storeCheck && !entry->writable) {
+ if (storeCheck && badWrite) {
// This would fault if this were a write, so return a page
// fault that reflects that happening.
- return new PageFault(vaddr, true, Write, inUser, false);
+ return std::make_shared<PageFault>(vaddr, true, Write, inUser,
+ false);
}
-
- DPRINTF(TLB, "Entry found with paddr %#x, "
- "doing protection checks.\n", entry->paddr);
- Addr paddr = entry->paddr | (vaddr & (entry->size-1));
+ Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes));
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
req->setPaddr(paddr);
+ if (entry->uncacheable)
+ req->setFlags(Request::UNCACHEABLE);
} else {
//Use the address which already has segmentation applied.
DPRINTF(TLB, "Paging disabled.\n");
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
req->setPaddr(vaddr);
}
- // Check for an access to the local APIC
-#if FULL_SYSTEM
- LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
- Addr baseAddr = localApicBase.base * PageBytes;
- Addr paddr = req->getPaddr();
- if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
- // The Intel developer's manuals say the below restrictions apply,
- // but the linux kernel, because of a compiler optimization, breaks
- // them.
- /*
- // Check alignment
- if (paddr & ((32/8) - 1))
- return new GeneralProtection(0);
- // Check access size
- if (req->getSize() != (32/8))
- return new GeneralProtection(0);
- */
- // Force the access to be uncacheable.
- req->setFlags(Request::UNCACHEABLE);
- req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
- }
-#endif
- return NoFault;
-};
+
+ return finalizePhysical(req, tc, mode);
+}
Fault
TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
translation->finish(fault, req, tc, mode);
}
-#if FULL_SYSTEM
-
-Tick
-TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
{
- return tc->getCpuPtr()->ticks(1);
+ panic("Not implemented\n");
+ return NoFault;
}
-Tick
-TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
+Walker *
+TLB::getWalker()
{
- return tc->getCpuPtr()->ticks(1);
+ return walker;
}
-#endif
-
void
TLB::serialize(std::ostream &os)
{
+ // Only store the entries in use.
+ uint32_t _size = size - freeList.size();
+ SERIALIZE_SCALAR(_size);
+ SERIALIZE_SCALAR(lruSeq);
+
+ uint32_t _count = 0;
+
+ for (uint32_t x = 0; x < size; x++) {
+ if (tlb[x].trieHandle != NULL) {
+ os << "\n[" << csprintf("%s.Entry%d", name(), _count) << "]\n";
+ tlb[x].serialize(os);
+ _count++;
+ }
+ }
}
void
TLB::unserialize(Checkpoint *cp, const std::string §ion)
{
+ // Do not allow to restore with a smaller tlb.
+ uint32_t _size;
+ UNSERIALIZE_SCALAR(_size);
+ if (_size > size) {
+ fatal("TLB size less than the one in checkpoint!");
+ }
+
+ UNSERIALIZE_SCALAR(lruSeq);
+
+ for (uint32_t x = 0; x < _size; x++) {
+ TlbEntry *newEntry = freeList.front();
+ freeList.pop_front();
+
+ newEntry->unserialize(cp, csprintf("%s.Entry%d", name(), x));
+ newEntry->trieHandle = trie.insert(newEntry->vaddr,
+ TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry);
+ }
+}
+
+BaseMasterPort *
+TLB::getMasterPort()
+{
+ return &walker->getMasterPort("port");
}
-/* end namespace X86ISA */ }
+} // namespace X86ISA
X86ISA::TLB *
X86TLBParams::create()
projects / gem5.git / blobdiff