* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
- * Redistribution and use of this software in source and binary forms,
- * with or without modification, are permitted provided that the
- * following conditions are met:
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
*
- * The software must be used only for Non-Commercial Use which means any
- * use which is NOT directed to receiving any direct monetary
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- * commercial advantage and providing services using the software for
- * commercial advantage.
- *
- * If you wish to use this software or functionality therein that may be
- * covered by patents for commercial use, please contact:
- * Director of Intellectual Property Licensing
- * Office of Strategy and Technology
- * Hewlett-Packard Company
- * 1501 Page Mill Road
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- * Redistributions of source code must retain the above copyright notice,
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+ * this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
#define __ARCH_X86_TLB_HH__
#include <list>
+#include <string>
+#include <vector>
+#include "arch/generic/tlb.hh"
+#include "arch/x86/regs/segment.hh"
#include "arch/x86/pagetable.hh"
-#include "arch/x86/segmentregs.hh"
-#include "config/full_system.hh"
+#include "base/trie.hh"
+#include "mem/mem_object.hh"
#include "mem/request.hh"
-#include "params/X86DTB.hh"
-#include "params/X86ITB.hh"
-#include "sim/faults.hh"
+#include "params/X86TLB.hh"
#include "sim/sim_object.hh"
class ThreadContext;
namespace X86ISA
{
- static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
+ class Walker;
- class TLB : public SimObject
+ class TLB : public BaseTLB
{
-#if !FULL_SYSTEM
protected:
- friend class FakeITLBFault;
- friend class FakeDTLBFault;
-#endif
+ friend class Walker;
+
+ typedef std::list<TlbEntry *> EntryList;
+
+ uint32_t configAddress;
+
public:
+
typedef X86TLBParams Params;
TLB(const Params *p);
- void dumpAll();
+ void takeOverFrom(BaseTLB *otlb) override {}
TlbEntry *lookup(Addr va, bool update_lru = true);
+ void setConfigAddress(uint32_t addr);
+
protected:
- int size;
- TlbEntry * tlb;
+ EntryList::iterator lookupIt(Addr va, bool update_lru = true);
- typedef std::list<TlbEntry *> EntryList;
- EntryList freeList;
- EntryList entryList;
+ Walker * walker;
- void insert(Addr vpn, TlbEntry &entry);
+ public:
+ Walker *getWalker();
- void invalidateAll();
+ void flushAll() override;
- void invalidateNonGlobal();
+ void flushNonGlobal();
- void demapPage(Addr va);
+ void demapPage(Addr va, uint64_t asn) override;
- public:
- // Checkpointing
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string §ion);
- };
+ protected:
+ uint32_t size;
- class ITB : public TLB
- {
- public:
- typedef X86ITBParams Params;
- ITB(const Params *p) : TLB(p)
- {
- }
+ std::vector<TlbEntry> tlb;
- Fault translate(RequestPtr &req, ThreadContext *tc);
+ EntryList freeList;
- friend class DTB;
- };
+ TlbEntryTrie trie;
+ uint64_t lruSeq;
+
+ Fault translateInt(RequestPtr req, ThreadContext *tc);
+
+ Fault translate(RequestPtr req, ThreadContext *tc,
+ Translation *translation, Mode mode,
+ bool &delayedResponse, bool timing);
- class DTB : public TLB
- {
public:
- typedef X86DTBParams Params;
- DTB(const Params *p) : TLB(p)
+
+ void evictLRU();
+
+ uint64_t
+ nextSeq()
{
+ return ++lruSeq;
}
- Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
-#if FULL_SYSTEM
- Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
- Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, Mode mode);
+ /** Stub function for compilation support of CheckerCPU. x86 ISA does
+ * not support Checker model at the moment
+ */
+ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+
+ /**
+ * Do post-translation physical address finalization.
+ *
+ * Some addresses, for example requests going to the APIC,
+ * need post-translation updates. Such physical addresses are
+ * remapped into a "magic" part of the physical address space
+ * by this method.
+ *
+ * @param req Request to updated in-place.
+ * @param tc Thread context that created the request.
+ * @param mode Request type (read/write/execute).
+ * @return A fault on failure, NoFault otherwise.
+ */
+ Fault finalizePhysical(RequestPtr req, ThreadContext *tc,
+ Mode mode) const;
+
+ TlbEntry * insert(Addr vpn, TlbEntry &entry);
// Checkpointing
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string §ion);
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
+
+ /**
+ * Get the table walker master port. This is used for
+ * migrating port connections during a CPU takeOverFrom()
+ * call. For architectures that do not have a table walker,
+ * NULL is returned, hence the use of a pointer rather than a
+ * reference. For X86 this method will always return a valid
+ * port pointer.
+ *
+ * @return A pointer to the walker master port
+ */
+ BaseMasterPort *getMasterPort() override;
};
}
projects / gem5.git / blobdiff