hsail: Fix disassembly of load instruction with 3 destination operands

[gem5.git] / src / arch / x86 / tlb.hh

diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 85bcead572b317d1a26cf66f81061d9491680f6b..53f61dcbc2023dab84a93f8d85b84d93e05d22b2 100644 (file)
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -44,15 +44,14 @@
 #include <string>
 #include <vector>
 
+#include "arch/generic/tlb.hh"
 #include "arch/x86/regs/segment.hh"
 #include "arch/x86/pagetable.hh"
 #include "base/trie.hh"
 #include "mem/mem_object.hh"
 #include "mem/request.hh"
 #include "params/X86TLB.hh"
-#include "sim/fault_fwd.hh"
 #include "sim/sim_object.hh"
-#include "sim/tlb.hh"
 
 class ThreadContext;
 class Packet;
@@ -75,7 +74,7 @@ namespace X86ISA
         typedef X86TLBParams Params;
         TLB(const Params *p);
 
-        void dumpAll();
+        void takeOverFrom(BaseTLB *otlb) override {}
 
         TlbEntry *lookup(Addr va, bool update_lru = true);
 
@@ -90,19 +89,18 @@ namespace X86ISA
       public:
         Walker *getWalker();
 
-        void invalidateAll();
+        void flushAll() override;
 
-        void invalidateNonGlobal();
+        void flushNonGlobal();
 
-        void demapPage(Addr va, uint64_t asn);
+        void demapPage(Addr va, uint64_t asn) override;
 
       protected:
-        int size;
+        uint32_t size;
 
-        TlbEntry * tlb;
+        std::vector<TlbEntry> tlb;
 
         EntryList freeList;
-        EntryList entryList;
 
         TlbEntryTrie trie;
         uint64_t lruSeq;
@@ -131,11 +129,27 @@ namespace X86ISA
          */
         Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
 
+        /**
+         * Do post-translation physical address finalization.
+         *
+         * Some addresses, for example requests going to the APIC,
+         * need post-translation updates. Such physical addresses are
+         * remapped into a "magic" part of the physical address space
+         * by this method.
+         *
+         * @param req Request to updated in-place.
+         * @param tc Thread context that created the request.
+         * @param mode Request type (read/write/execute).
+         * @return A fault on failure, NoFault otherwise.
+         */
+        Fault finalizePhysical(RequestPtr req, ThreadContext *tc,
+                               Mode mode) const;
+
         TlbEntry * insert(Addr vpn, TlbEntry &entry);
 
         // Checkpointing
-        virtual void serialize(std::ostream &os);
-        virtual void unserialize(Checkpoint *cp, const std::string &section);
+        void serialize(CheckpointOut &cp) const override;
+        void unserialize(CheckpointIn &cp) override;
 
         /**
          * Get the table walker master port. This is used for
@@ -147,7 +161,7 @@ namespace X86ISA
          *
          * @return A pointer to the walker master port
          */
-        virtual BaseMasterPort *getMasterPort();
+        BaseMasterPort *getMasterPort() override;
     };
 }