hsail: Fix disassembly of load instruction with 3 destination operands

[gem5.git] / src / arch / x86 / tlb.hh

diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 8a6b7a00a0c8ffcb50d5d170f64e7f2f601e64c9..53f61dcbc2023dab84a93f8d85b84d93e05d22b2 100644 (file)
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -41,17 +41,16 @@
 #define __ARCH_X86_TLB_HH__
 
 #include <list>
-#include <vector>
 #include <string>
+#include <vector>
 
+#include "arch/generic/tlb.hh"
+#include "arch/x86/regs/segment.hh"
 #include "arch/x86/pagetable.hh"
-#include "arch/x86/segmentregs.hh"
-#include "config/full_system.hh"
+#include "base/trie.hh"
 #include "mem/mem_object.hh"
 #include "mem/request.hh"
 #include "params/X86TLB.hh"
-#include "sim/faults.hh"
-#include "sim/tlb.hh"
 #include "sim/sim_object.hh"
 
 class ThreadContext;
@@ -75,7 +74,7 @@ namespace X86ISA
         typedef X86TLBParams Params;
         TLB(const Params *p);
 
-        void dumpAll();
+        void takeOverFrom(BaseTLB *otlb) override {}
 
         TlbEntry *lookup(Addr va, bool update_lru = true);
 
@@ -85,26 +84,26 @@ namespace X86ISA
 
         EntryList::iterator lookupIt(Addr va, bool update_lru = true);
 
-#if FULL_SYSTEM
-      protected:
-
         Walker * walker;
-#endif
 
       public:
-        void invalidateAll();
+        Walker *getWalker();
+
+        void flushAll() override;
 
-        void invalidateNonGlobal();
+        void flushNonGlobal();
 
-        void demapPage(Addr va, uint64_t asn);
+        void demapPage(Addr va, uint64_t asn) override;
 
       protected:
-        int size;
+        uint32_t size;
 
-        TlbEntry * tlb;
+        std::vector<TlbEntry> tlb;
 
         EntryList freeList;
-        EntryList entryList;
+
+        TlbEntryTrie trie;
+        uint64_t lruSeq;
 
         Fault translateInt(RequestPtr req, ThreadContext *tc);
 
@@ -114,20 +113,55 @@ namespace X86ISA
 
       public:
 
+        void evictLRU();
+
+        uint64_t
+        nextSeq()
+        {
+            return ++lruSeq;
+        }
+
         Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
         void translateTiming(RequestPtr req, ThreadContext *tc,
                 Translation *translation, Mode mode);
-
-#if FULL_SYSTEM
-        Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
-        Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
+        /** Stub function for compilation support of CheckerCPU. x86 ISA does
+         *  not support Checker model at the moment
+         */
+        Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+
+        /**
+         * Do post-translation physical address finalization.
+         *
+         * Some addresses, for example requests going to the APIC,
+         * need post-translation updates. Such physical addresses are
+         * remapped into a "magic" part of the physical address space
+         * by this method.
+         *
+         * @param req Request to updated in-place.
+         * @param tc Thread context that created the request.
+         * @param mode Request type (read/write/execute).
+         * @return A fault on failure, NoFault otherwise.
+         */
+        Fault finalizePhysical(RequestPtr req, ThreadContext *tc,
+                               Mode mode) const;
 
         TlbEntry * insert(Addr vpn, TlbEntry &entry);
 
         // Checkpointing
-        virtual void serialize(std::ostream &os);
-        virtual void unserialize(Checkpoint *cp, const std::string &section);
+        void serialize(CheckpointOut &cp) const override;
+        void unserialize(CheckpointIn &cp) override;
+
+        /**
+         * Get the table walker master port. This is used for
+         * migrating port connections during a CPU takeOverFrom()
+         * call. For architectures that do not have a table walker,
+         * NULL is returned, hence the use of a pointer rather than a
+         * reference. For X86 this method will always return a valid
+         * port pointer.
+         *
+         * @return A pointer to the walker master port
+         */
+        BaseMasterPort *getMasterPort() override;
     };
 }