#ifndef __ARCH_X86_TLB_HH__
#define __ARCH_X86_TLB_HH__
-#include "config/full_system.hh"
-
-#if FULL_SYSTEM
+#include <list>
+#include <vector>
+#include <string>
-#include "arch/segmentregs.hh"
+#include "arch/x86/pagetable.hh"
+#include "arch/x86/segmentregs.hh"
+#include "config/full_system.hh"
+#include "mem/mem_object.hh"
#include "mem/request.hh"
#include "params/X86DTB.hh"
#include "params/X86ITB.hh"
#include "sim/faults.hh"
+#include "sim/tlb.hh"
#include "sim/sim_object.hh"
class ThreadContext;
namespace X86ISA
{
+ class Walker;
+
static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
- struct TlbEntry
+ class TLB;
+
+ class TLB : public BaseTLB
{
- Addr pageStart;
- TlbEntry() {}
- TlbEntry(Addr paddr) : pageStart(paddr) {}
+ protected:
+ friend class FakeITLBFault;
+ friend class FakeDTLBFault;
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string §ion);
- };
+ typedef std::list<TlbEntry *> EntryList;
-class TLB : public SimObject
-{
- public:
- typedef X86TLBParams Params;
- TLB(const Params *p);
+ bool _allowNX;
+ uint32_t configAddress;
- void dumpAll();
+ public:
+ bool allowNX() const
+ {
+ return _allowNX;
+ }
- // Checkpointing
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string §ion);
-};
+ typedef X86TLBParams Params;
+ TLB(const Params *p);
-class ITB : public TLB
-{
- public:
- typedef X86ITBParams Params;
- ITB(const Params *p) : TLB(p)
- {
- }
+ void dumpAll();
- Fault translate(RequestPtr &req, ThreadContext *tc);
+ TlbEntry *lookup(Addr va, bool update_lru = true);
- friend class DTB;
-};
+ void setConfigAddress(uint32_t addr);
-class DTB : public TLB
-{
- public:
- typedef X86DTBParams Params;
- DTB(const Params *p) : TLB(p)
- {
- }
+ protected:
+
+ EntryList::iterator lookupIt(Addr va, bool update_lru = true);
- Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
#if FULL_SYSTEM
- Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
- Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
+ protected:
+
+ Walker * walker;
+
+ void walk(ThreadContext * _tc, Addr vaddr);
#endif
- // Checkpointing
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string §ion);
-};
+ public:
+ void invalidateAll();
-}
+ void invalidateNonGlobal();
-#else
+ void demapPage(Addr va, uint64_t asn);
-#include <iostream>
+ protected:
+ int size;
-#include "arch/x86/segmentregs.hh"
-#include "sim/host.hh"
-#include "sim/tlb.hh"
+ TlbEntry * tlb;
-class Checkpoint;
+ EntryList freeList;
+ EntryList entryList;
-namespace X86ISA
-{
- static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
+ template<class TlbFault>
+ Fault translate(RequestPtr &req, ThreadContext *tc,
+ bool write, bool execute);
- struct TlbEntry
- {
- Addr pageStart;
- TlbEntry() {}
- TlbEntry(Addr paddr) : pageStart(paddr) {}
+ public:
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string §ion);
+ void insert(Addr vpn, TlbEntry &entry);
+
+ // Checkpointing
+ virtual void serialize(std::ostream &os);
+ virtual void unserialize(Checkpoint *cp, const std::string §ion);
};
- class ITB : public GenericTLB
+ class ITB : public TLB
{
public:
- ITB(const Params *p) : GenericTLB(p)
- {}
+ typedef X86ITBParams Params;
+ ITB(const Params *p) : TLB(p)
+ {
+ _allowNX = false;
+ }
+
+ Fault translate(RequestPtr &req, ThreadContext *tc);
+
+ friend class DTB;
};
- class DTB : public GenericTLB
+ class DTB : public TLB
{
public:
- DTB(const Params *p) : GenericTLB(p)
- {}
- };
-};
-
+ typedef X86DTBParams Params;
+ DTB(const Params *p) : TLB(p)
+ {
+ _allowNX = true;
+ }
+ Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+#if FULL_SYSTEM
+ Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
+ Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
#endif
+ // Checkpointing
+ virtual void serialize(std::ostream &os);
+ virtual void unserialize(Checkpoint *cp, const std::string §ion);
+ };
+}
+
#endif // __ARCH_X86_TLB_HH__