X86: Compute PCI config addresses correctly.

[gem5.git] / src / arch / x86 / tlb.hh

diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 4cf65ac081ef00ad6cfb70c0a1c5042b59b567b6..89b965e971177f792d2d567ac2e4d43da445d636 100644 (file)
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -58,39 +58,130 @@
 #ifndef __ARCH_X86_TLB_HH__
 #define __ARCH_X86_TLB_HH__
 
-#include <iostream>
+#include <list>
+#include <vector>
 #include <string>
 
-#include "sim/host.hh"
+#include "arch/x86/pagetable.hh"
+#include "arch/x86/segmentregs.hh"
+#include "config/full_system.hh"
+#include "mem/mem_object.hh"
+#include "mem/request.hh"
+#include "params/X86DTB.hh"
+#include "params/X86ITB.hh"
+#include "sim/faults.hh"
 #include "sim/tlb.hh"
+#include "sim/sim_object.hh"
 
-class Checkpoint;
+class ThreadContext;
+class Packet;
 
 namespace X86ISA
 {
-    struct TlbEntry
+    class Walker;
+
+    static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
+
+    class TLB;
+
+    class TLB : public BaseTLB
     {
-        Addr pageStart;
-        TlbEntry() {}
-        TlbEntry(Addr paddr) : pageStart(paddr) {}
+      protected:
+        friend class FakeITLBFault;
+        friend class FakeDTLBFault;
+
+        typedef std::list<TlbEntry *> EntryList;
+
+        bool _allowNX;
+        uint32_t configAddress;
+
+      public:
+        bool allowNX() const
+        {
+            return _allowNX;
+        }
+
+        typedef X86TLBParams Params;
+        TLB(const Params *p);
+
+        void dumpAll();
+
+        TlbEntry *lookup(Addr va, bool update_lru = true);
+
+        void setConfigAddress(uint32_t addr);
+
+      protected:
+
+        EntryList::iterator lookupIt(Addr va, bool update_lru = true);
+
+#if FULL_SYSTEM
+      protected:
+
+        Walker * walker;
 
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
+        void walk(ThreadContext * _tc, Addr vaddr);
+#endif
+
+      public:
+        void invalidateAll();
+
+        void invalidateNonGlobal();
+
+        void demapPage(Addr va, uint64_t asn);
+
+      protected:
+        int size;
+
+        TlbEntry * tlb;
+
+        EntryList freeList;
+        EntryList entryList;
+
+        template<class TlbFault>
+        Fault translate(RequestPtr &req, ThreadContext *tc,
+                bool write, bool execute);
+
+      public:
+
+        void insert(Addr vpn, TlbEntry &entry);
+
+        // Checkpointing
+        virtual void serialize(std::ostream &os);
+        virtual void unserialize(Checkpoint *cp, const std::string &section);
     };
 
-    class ITB : public GenericITB<false, false>
+    class ITB : public TLB
     {
       public:
-        ITB(const std::string &name) : GenericITB<false, false>(name)
-        {}
+        typedef X86ITBParams Params;
+        ITB(const Params *p) : TLB(p)
+        {
+            _allowNX = false;
+        }
+
+        Fault translate(RequestPtr &req, ThreadContext *tc);
+
+        friend class DTB;
     };
 
-    class DTB : public GenericDTB<false, false>
+    class DTB : public TLB
     {
       public:
-        DTB(const std::string &name) : GenericDTB<false, false>(name)
-        {}
+        typedef X86DTBParams Params;
+        DTB(const Params *p) : TLB(p)
+        {
+            _allowNX = true;
+        }
+        Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+#if FULL_SYSTEM
+        Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
+        Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
+#endif
+
+        // Checkpointing
+        virtual void serialize(std::ostream &os);
+        virtual void unserialize(Checkpoint *cp, const std::string &section);
     };
-};
+}
 
 #endif // __ARCH_X86_TLB_HH__