#include <list>
#include <vector>
-#include <string>
+#include "arch/generic/tlb.hh"
#include "arch/x86/pagetable.hh"
-#include "arch/x86/regs/segment.hh"
-#include "config/full_system.hh"
-#include "mem/mem_object.hh"
+#include "base/trie.hh"
#include "mem/request.hh"
#include "params/X86TLB.hh"
-#include "sim/fault_fwd.hh"
-#include "sim/tlb.hh"
-#include "sim/sim_object.hh"
class ThreadContext;
-class Packet;
namespace X86ISA
{
typedef X86TLBParams Params;
TLB(const Params *p);
- void dumpAll();
+ void takeOverFrom(BaseTLB *otlb) override {}
TlbEntry *lookup(Addr va, bool update_lru = true);
EntryList::iterator lookupIt(Addr va, bool update_lru = true);
-#if FULL_SYSTEM
- protected:
-
Walker * walker;
+
public:
Walker *getWalker();
-#endif
- public:
- void invalidateAll();
+ void flushAll() override;
- void invalidateNonGlobal();
+ void flushNonGlobal();
- void demapPage(Addr va, uint64_t asn);
+ void demapPage(Addr va, uint64_t asn) override;
protected:
- int size;
+ uint32_t size;
- TlbEntry * tlb;
+ std::vector<TlbEntry> tlb;
EntryList freeList;
- EntryList entryList;
- Fault translateInt(RequestPtr req, ThreadContext *tc);
+ TlbEntryTrie trie;
+ uint64_t lruSeq;
- Fault translate(RequestPtr req, ThreadContext *tc,
+ // Statistics
+ Stats::Scalar rdAccesses;
+ Stats::Scalar wrAccesses;
+ Stats::Scalar rdMisses;
+ Stats::Scalar wrMisses;
+
+ Fault translateInt(const RequestPtr &req, ThreadContext *tc);
+
+ Fault translate(const RequestPtr &req, ThreadContext *tc,
Translation *translation, Mode mode,
bool &delayedResponse, bool timing);
public:
- Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
- void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, Mode mode);
-
-#if FULL_SYSTEM
- Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
- Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
-
- TlbEntry * insert(Addr vpn, TlbEntry &entry);
+ void evictLRU();
+
+ uint64_t
+ nextSeq()
+ {
+ return ++lruSeq;
+ }
+
+ Fault translateAtomic(
+ const RequestPtr &req, ThreadContext *tc, Mode mode) override;
+ void translateTiming(
+ const RequestPtr &req, ThreadContext *tc,
+ Translation *translation, Mode mode) override;
+
+ /**
+ * Do post-translation physical address finalization.
+ *
+ * Some addresses, for example requests going to the APIC,
+ * need post-translation updates. Such physical addresses are
+ * remapped into a "magic" part of the physical address space
+ * by this method.
+ *
+ * @param req Request to updated in-place.
+ * @param tc Thread context that created the request.
+ * @param mode Request type (read/write/execute).
+ * @return A fault on failure, NoFault otherwise.
+ */
+ Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc,
+ Mode mode) const override;
+
+ TlbEntry *insert(Addr vpn, const TlbEntry &entry);
+
+ /*
+ * Function to register Stats
+ */
+ void regStats() override;
// Checkpointing
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string §ion);
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
+
+ /**
+ * Get the table walker port. This is used for
+ * migrating port connections during a CPU takeOverFrom()
+ * call. For architectures that do not have a table walker,
+ * NULL is returned, hence the use of a pointer rather than a
+ * reference. For X86 this method will always return a valid
+ * port pointer.
+ *
+ * @return A pointer to the walker port
+ */
+ Port *getTableWalkerPort() override;
};
}