Merge zizzer.eecs.umich.edu:/bk/newmem

[gem5.git] / src / arch / x86 / types.hh

diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index 583f03d553d4d2089f53b802cfb220b34fd6fa2c..22525835864ef0596a6dc389c329ce03eb89972a 100644 (file)
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -61,76 +61,137 @@
 #include <inttypes.h>
 #include <iostream>
 
+#include "base/bitfield.hh"
+#include "base/cprintf.hh"
+
 namespace X86ISA
 {
     //This really determines how many bytes are passed to the predecoder.
     typedef uint64_t MachInst;
 
     enum Prefixes {
-        NoOverride = 0,
-        CSOverride = 1,
-        DSOverride = 2,
-        ESOverride = 3,
-        FSOverride = 4,
-        GSOverride = 5,
-        SSOverride = 6,
-        //The Rex prefix obviously doesn't fit in with the above, but putting
-        //it here lets us save double the space the enums take up.
-        Rex = 7,
+        NoOverride,
+        CSOverride,
+        DSOverride,
+        ESOverride,
+        FSOverride,
+        GSOverride,
+        SSOverride,
+        RexPrefix,
+        OperandSizeOverride,
+        AddressSizeOverride,
+        Lock,
+        Rep,
+        Repne
+    };
+
+    BitUnion8(LegacyPrefixVector)
+        Bitfield<7> repne;
+        Bitfield<6> rep;
+        Bitfield<5> lock;
+        Bitfield<4> addr;
+        Bitfield<3> op;
         //There can be only one segment override, so they share the
         //first 3 bits in the legacyPrefixes bitfield.
-        SegmentOverride = 0x7,
-        OperandSizeOverride = 8,
-        AddressSizeOverride = 16,
-        Lock = 32,
-        Rep = 64,
-        Repne = 128
-    };
+        Bitfield<2,0> seg;
+    EndBitUnion(LegacyPrefixVector)
+
+    BitUnion8(ModRM)
+        Bitfield<7,6> mod;
+        Bitfield<5,3> reg;
+        Bitfield<2,0> rm;
+    EndBitUnion(ModRM)
+
+    BitUnion8(Sib)
+        Bitfield<7,6> scale;
+        Bitfield<5,3> index;
+        Bitfield<2,0> base;
+    EndBitUnion(Sib)
+
+    BitUnion8(Rex)
+        Bitfield<3> w;
+        Bitfield<2> r;
+        Bitfield<1> x;
+        Bitfield<0> b;
+    EndBitUnion(Rex)
+
+    BitUnion8(Opcode)
+        Bitfield<7,3> top5;
+        Bitfield<2,0> bottom3;
+    EndBitUnion(Opcode)
 
     //The intermediate structure the x86 predecoder returns.
     struct ExtMachInst
     {
-      public: //XXX These should be hidden in the future
-
-        uint8_t legacyPrefixes;
-        uint8_t rexPrefix;
-        //Right now, we ignore that this can be 3 in
-        //some cases
-        uint8_t numOpcodes;
-        //This will need to be decoded specially later
-        bool is3dnow;
-        uint8_t opcode;
+        //Prefixes
+        LegacyPrefixVector legacy;
+        Rex rex;
+        //This holds all of the bytes of the opcode
+        struct
+        {
+            //The number of bytes in this opcode. Right now, we ignore that
+            //this can be 3 in some cases
+            uint8_t num;
+            //The first byte detected in a 2+ byte opcode. Should be 0xF0.
+            uint8_t prefixA;
+            //The second byte detected in a 3+ byte opcode. Could be 0xF0 for
+            //3dnow instructions, or 0x38-0x3F for some SSE instructions.
+            uint8_t prefixB;
+            //The main opcode byte. The highest addressed byte in the opcode.
+            Opcode op;
+        } opcode;
+        //Modifier bytes
+        ModRM modRM;
+        uint8_t sib;
+        //Immediate fields
         uint64_t immediate;
         uint64_t displacement;
 
-      public:
-
-        //These are to pacify the decoder for now. This will go away once
-        //it can handle non integer inputs, and in the mean time allow me to
-        //excercise the predecoder a little.
-        operator unsigned int()
-        {
-            return 0;
-        }
-
-        ExtMachInst(unsigned int)
-        {;}
-
-        ExtMachInst()
-        {;}
+        //The effective operand size.
+        uint8_t opSize;
+        //The effective address size.
+        uint8_t addrSize;
     };
 
     inline static std::ostream &
         operator << (std::ostream & os, const ExtMachInst & emi)
     {
-        os << "{X86 ExtMachInst}";
+        ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
+                     "op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t"
+                           "prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t"
+                     "modRM = %#x,\n\tsib = %#x,\n\t"
+                     "immediate = %#x,\n\tdisplacement = %#x\n}\n",
+                     emi.legacy, (uint8_t)emi.rex,
+                     emi.opcode.num, emi.opcode.op,
+                     emi.opcode.prefixA, emi.opcode.prefixB,
+                     (uint8_t)emi.modRM, (uint8_t)emi.sib,
+                     emi.immediate, emi.displacement);
         return os;
     }
 
     inline static bool
         operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
     {
-        //Since this is empty, it's always equal
+        if(emi1.legacy != emi2.legacy)
+            return false;
+        if(emi1.rex != emi2.rex)
+            return false;
+        if(emi1.opcode.num != emi2.opcode.num)
+            return false;
+        if(emi1.opcode.op != emi2.opcode.op)
+            return false;
+        if(emi1.opcode.prefixA != emi2.opcode.prefixA)
+            return false;
+        if(emi1.opcode.prefixB != emi2.opcode.prefixB)
+            return false;
+        if(emi1.modRM != emi2.modRM)
+            return false;
+        if(emi1.sib != emi2.sib)
+            return false;
+        if(emi1.immediate != emi2.immediate)
+            return false;
+        if(emi1.displacement != emi2.displacement)
+            return false;
         return true;
     }