* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
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+ * The license below extends only to copyright in the software and shall
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+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
#ifndef __ARCH_X86_UTILITY_HH__
#define __ARCH_X86_UTILITY_HH__
+#include "arch/x86/regs/misc.hh"
#include "arch/x86/types.hh"
#include "base/hashmap.hh"
#include "base/misc.hh"
+#include "base/types.hh"
+#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
-#include "sim/host.hh"
+#include "sim/full_system.hh"
class ThreadContext;
-namespace __hash_namespace {
- template<>
- struct hash<X86ISA::ExtMachInst> {
- size_t operator()(const X86ISA::ExtMachInst &emi) const {
- return (((uint64_t)emi.legacy << 56) |
- ((uint64_t)emi.rex << 48) |
- ((uint64_t)emi.modRM << 40) |
- ((uint64_t)emi.sib << 32) |
- ((uint64_t)emi.opcode.num << 24) |
- ((uint64_t)emi.opcode.prefixA << 16) |
- ((uint64_t)emi.opcode.prefixB << 8) |
- ((uint64_t)emi.opcode.op)) ^
- emi.immediate ^ emi.displacement;
- };
- };
-}
-
namespace X86ISA
{
- static inline bool
- inUserMode(ThreadContext *tc)
- {
- return false;
- }
-
- inline bool isCallerSaveIntegerRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
- inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
- inline bool isCallerSaveFloatRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
- inline bool isCalleeSaveFloatRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
- // Instruction address compression hooks
- inline Addr realPCToFetchPC(const Addr &addr)
+ inline PCState
+ buildRetPC(const PCState &curPC, const PCState &callPC)
{
- return addr;
+ PCState retPC = callPC;
+ retPC.uEnd();
+ return retPC;
}
- inline Addr fetchPCToRealPC(const Addr &addr)
- {
- return addr;
- }
+ uint64_t
+ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
- // the size of "fetched" instructions (not necessarily the size
- // of real instructions for PISA)
- inline size_t fetchInstSize()
+ static inline bool
+ inUserMode(ThreadContext *tc)
{
- return sizeof(MachInst);
+ if (!FullSystem) {
+ return true;
+ } else {
+ HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
+ return m5reg.cpl == 3;
+ }
}
/**
template <class TC>
void zeroRegisters(TC *tc);
- inline void initCPU(ThreadContext *tc, int cpuId)
+ void initCPU(ThreadContext *tc, int cpuId);
+
+ void startupCPU(ThreadContext *tc, int cpuId);
+
+ void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+ void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
+ void skipFunction(ThreadContext *tc);
+
+ inline void
+ advancePC(PCState &pc, const StaticInstPtr inst)
{
- panic("initCPU not implemented!\n");
+ inst->advancePC(pc);
}
- inline void startupCPU(ThreadContext *tc, int cpuId)
+ inline uint64_t
+ getExecutingAsid(ThreadContext *tc)
{
- tc->activate(0);
+ return 0;
}
-};
+
+}
#endif // __ARCH_X86_UTILITY_HH__