types: Move stuff for global types into src/base/types.hh

[gem5.git] / src / arch / x86 / x86_traits.hh

diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh
index 33ec133728700c1ced61c3b7244c4e5812c29cbe..381695c4064436aeb512d1ffb7253c55eea1388c 100644 (file)
--- a/src/arch/x86/x86_traits.hh
+++ b/src/arch/x86/x86_traits.hh
@@ -58,6 +58,10 @@
 #ifndef __ARCH_X86_X86TRAITS_HH__
 #define __ARCH_X86_X86TRAITS_HH__
 
+#include <assert.h>
+
+#include "base/types.hh"
+
 namespace X86ISA
 {
     const int NumMicroIntRegs = 16;
@@ -80,6 +84,45 @@ namespace X86ISA
 
     const int NumSegments = 6;
     const int NumSysSegments = 4;
+
+    const Addr IntAddrPrefixMask = ULL(0xffffffff00000000);
+    const Addr IntAddrPrefixCPUID = ULL(0x100000000);
+    const Addr IntAddrPrefixMSR = ULL(0x200000000);
+    const Addr IntAddrPrefixIO = ULL(0x300000000);
+
+    const Addr PhysAddrPrefixIO = ULL(0x8000000000000000);
+    const Addr PhysAddrPrefixPciConfig = ULL(0xC000000000000000);
+    const Addr PhysAddrPrefixLocalAPIC = ULL(0x2000000000000000);
+    const Addr PhysAddrPrefixInterrupts = ULL(0xA000000000000000);
+    // Each APIC gets two pages. One page is used for local apics to field
+    // accesses from the CPU, and the other is for all APICs to communicate.
+    const Addr PhysAddrAPICRangeSize = 1 << 12;
+
+    static inline Addr
+    x86IOAddress(const uint32_t port)
+    {
+        return PhysAddrPrefixIO | port;
+    }
+
+    static inline Addr
+    x86PciConfigAddress(const uint32_t addr)
+    {
+        return PhysAddrPrefixPciConfig | addr;
+    }
+
+    static inline Addr
+    x86LocalAPICAddress(const uint8_t id, const uint16_t addr)
+    {
+        assert(addr < (1 << 12));
+        return PhysAddrPrefixLocalAPIC | (id * (1 << 12)) | addr;
+    }
+
+    static inline Addr
+    x86InterruptAddress(const uint8_t id, const uint16_t addr)
+    {
+        assert(addr < PhysAddrAPICRangeSize);
+        return PhysAddrPrefixInterrupts | (id * PhysAddrAPICRangeSize) | addr;
+    }
 }
 
 #endif //__ARCH_X86_X86TRAITS_HH__