* Authors: Gabe Black
*/
-#include "sim/host.hh"
-
#ifndef __ARCH_X86_X86TRAITS_HH__
#define __ARCH_X86_X86TRAITS_HH__
+#include <assert.h>
+
+#include "base/types.hh"
+
namespace X86ISA
{
const int NumMicroIntRegs = 16;
const Addr IntAddrPrefixMask = ULL(0xffffffff00000000);
const Addr IntAddrPrefixCPUID = ULL(0x100000000);
const Addr IntAddrPrefixMSR = ULL(0x200000000);
+ const Addr IntAddrPrefixIO = ULL(0x300000000);
+
+ const Addr PhysAddrPrefixIO = ULL(0x8000000000000000);
+ const Addr PhysAddrPrefixPciConfig = ULL(0xC000000000000000);
+ const Addr PhysAddrPrefixLocalAPIC = ULL(0x2000000000000000);
+ const Addr PhysAddrPrefixInterrupts = ULL(0xA000000000000000);
+ // Each APIC gets two pages. One page is used for local apics to field
+ // accesses from the CPU, and the other is for all APICs to communicate.
+ const Addr PhysAddrAPICRangeSize = 1 << 12;
+
+ static inline Addr
+ x86IOAddress(const uint32_t port)
+ {
+ return PhysAddrPrefixIO | port;
+ }
+
+ static inline Addr
+ x86PciConfigAddress(const uint32_t addr)
+ {
+ return PhysAddrPrefixPciConfig | addr;
+ }
+
+ static inline Addr
+ x86LocalAPICAddress(const uint8_t id, const uint16_t addr)
+ {
+ assert(addr < (1 << 12));
+ return PhysAddrPrefixLocalAPIC | (id * (1 << 12)) | addr;
+ }
+
+ static inline Addr
+ x86InterruptAddress(const uint8_t id, const uint16_t addr)
+ {
+ assert(addr < PhysAddrAPICRangeSize);
+ return PhysAddrPrefixInterrupts | (id * PhysAddrAPICRangeSize) | addr;
+ }
}
#endif //__ARCH_X86_X86TRAITS_HH__