ARM: Improve memory instruction disassembly.

[gem5.git] / src / base / bigint.hh

diff --git a/src/base/bigint.hh b/src/base/bigint.hh
index aa60eeb04e7656d0e69cf6dd1e867a667eb69336..d6068423144d690e5504d9448be1e9f2edef423d 100644 (file)
--- a/src/base/bigint.hh
+++ b/src/base/bigint.hh
@@ -28,24 +28,70 @@
  * Authors: Ali Saidi
  */
 
+#include "base/misc.hh"
+
+#include <iostream>
+
 #ifndef __BASE_BIGINT_HH__
 #define __BASE_BIGINT_HH__
 // Create a couple of large int types for atomic reads
 struct m5_twin64_t {
     uint64_t a;
     uint64_t b;
+    m5_twin64_t()
+    {}
+    m5_twin64_t(const uint64_t x)
+    {
+        a = x;
+        b = x;
+    }
     inline m5_twin64_t& operator=(const uint64_t x)
     {
         a = x;
         b = x;
         return *this;
     }
+
+    operator uint64_t()
+    {
+        panic("Tried to cram a twin64_t into an integer!\n");
+        return a;
+    }
+};
+
+struct m5_twin32_t {
+    uint32_t a;
+    uint32_t b;
+    m5_twin32_t()
+    {}
+    m5_twin32_t(const uint32_t x)
+    {
+        a = x;
+        b = x;
+    }
+    inline m5_twin32_t& operator=(const uint32_t x)
+    {
+        a = x;
+        b = x;
+        return *this;
+    }
+
+    operator uint32_t()
+    {
+        panic("Tried to cram a twin32_t into an integer!\n");
+        return a;
+    }
 };
 
+
 // This is for twin loads (two 64 bit values), not 1 128 bit value (as far as
 // endian conversion is concerned!
 typedef m5_twin64_t Twin64_t;
+typedef m5_twin32_t Twin32_t;
 
+// Output operator overloads
+std::ostream & operator << (std::ostream & os, const Twin64_t & t);
+std::ostream & operator << (std::ostream & os, const Twin32_t & t);
 
 #endif // __BASE_BIGINT_HH__