if (c->execute.file != QFILE_NULL) {
last_inst->dst.index = qregs[chan].index;
- /* Set the flags to the current exec mask. To insert
- * the flags push, we temporarily remove our SSA
- * instruction.
+ /* Set the flags to the current exec mask.
*/
- list_del(&last_inst->link);
+ c->cursor = vir_before_inst(last_inst);
vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
- list_addtail(&last_inst->link,
- &c->cur_block->instructions);
+ c->cursor = vir_after_inst(last_inst);
vir_set_cond(last_inst, V3D_QPU_COND_IFA);
last_inst->cond_is_exec_mask = true;
ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
unsigned src)
{
- assert(util_is_power_of_two(instr->dest.write_mask));
+ assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
unsigned chan = ffs(instr->dest.write_mask) - 1;
struct qreg r = ntq_get_src(c, instr->src[src].src,
instr->src[src].swizzle[chan]);
vir_uniform_f(c, 0.0));
}
-static struct qreg
-ntq_umul(struct v3d_compile *c, struct qreg src0, struct qreg src1)
-{
- vir_MULTOP(c, src0, src1);
- return vir_UMUL24(c, src0, src1);
-}
-
static struct qreg
ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
{
emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
uint8_t swizzle)
{
- struct qreg vary = vir_reg(QFILE_VARY, ~0);
+ struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
+ struct qreg vary;
+ if (c->devinfo->ver >= 41) {
+ struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
+ c->undef, c->undef);
+ ldvary->qpu.sig.ldvary = true;
+ vary = vir_emit_def(c, ldvary);
+ } else {
+ vir_NOP(c)->qpu.sig.ldvary = true;
+ vary = r3;
+ }
+
/* For gl_PointCoord input or distance along a line, we'll be called
* with no nir_variable, and we don't count toward VPM size so we
* don't track an input slot.
/* FALLTHROUGH */
case INTERP_MODE_SMOOTH:
if (var->data.centroid) {
+ BITSET_SET(c->centroid_flags, i);
return vir_FADD(c, vir_FMUL(c, vary,
c->payload_w_centroid), r5);
} else {
return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
}
case INTERP_MODE_NOPERSPECTIVE:
- /* C appears after the mov from the varying.
- XXX: improve ldvary setup.
- */
+ BITSET_SET(c->noperspective_flags, i);
return vir_FADD(c, vir_MOV(c, vary), r5);
case INTERP_MODE_FLAT:
BITSET_SET(c->flat_shade_flags, i);
nir_alu_instr *sel_instr)
{
struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
- struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
+ struct qreg src1;
+ if (nir_op_infos[compare_instr->op].num_inputs > 1)
+ src1 = ntq_get_alu_src(c, compare_instr, 1);
bool cond_invert = false;
switch (compare_instr->op) {
result = vir_NOT(c, src[0]);
break;
+ case nir_op_ufind_msb:
+ result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
+ break;
+
case nir_op_imul:
- result = ntq_umul(c, src[0], src[1]);
+ result = vir_UMUL(c, src[0], src[1]);
break;
case nir_op_seq:
result = vir_FDY(c, src[0]);
break;
+ case nir_op_uadd_carry:
+ vir_PF(c, vir_ADD(c, src[0], src[1]), V3D_QPU_PF_PUSHC);
+ result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
+ vir_uniform_ui(c, ~0),
+ vir_uniform_ui(c, 0)));
+ break;
+
default:
fprintf(stderr, "unknown NIR ALU inst: ");
nir_print_instr(&instr->instr, stderr);
/* We have a scalar result, so the instruction should only have a
* single channel written to.
*/
- assert(util_is_power_of_two(instr->dest.write_mask));
+ assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
ntq_store_dest(c, &instr->dest.dest,
ffs(instr->dest.write_mask) - 1, result);
}
has_any_tlb_color_write = true;
}
+ if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
+ struct nir_variable *var = c->output_color_var[0];
+ struct qreg *color = &c->outputs[var->data.driver_location * 4];
+
+ vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
+ vir_AND(c,
+ vir_MSF(c),
+ vir_FTOC(c, color[3])));
+ }
+
if (c->output_position_index != -1) {
struct qinst *inst = vir_MOV_dest(c,
vir_reg(QFILE_TLBU, 0),
TLB_TYPE_DEPTH |
TLB_DEPTH_TYPE_PER_PIXEL |
0xffffff00);
- } else if (c->s->info.fs.uses_discard || !has_any_tlb_color_write) {
+ } else if (c->s->info.fs.uses_discard ||
+ c->fs_key->sample_alpha_to_coverage ||
+ !has_any_tlb_color_write) {
/* Emit passthrough Z if it needed to be delayed until shader
* end due to potential discards.
*
conf |= TLB_SAMPLE_MODE_PER_PIXEL;
conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
+ if (c->fs_key->swap_color_rb & (1 << rt))
+ num_components = MAX2(num_components, 3);
+
assert(num_components != 0);
switch (glsl_get_base_type(var->type)) {
case GLSL_TYPE_UINT:
case GLSL_TYPE_INT:
- conf |= TLB_TYPE_I32_COLOR;
+ /* The F32 vs I32 distinction was dropped in 4.2. */
+ if (c->devinfo->ver < 42)
+ conf |= TLB_TYPE_I32_COLOR;
+ else
+ conf |= TLB_TYPE_F32_COLOR;
conf |= ((num_components - 1) <<
TLB_VEC_SIZE_MINUS_1_SHIFT);
struct qreg b = color[2];
struct qreg a = color[3];
- if (c->fs_key->f32_color_rb) {
+ if (c->fs_key->f32_color_rb & (1 << rt)) {
conf |= TLB_TYPE_F32_COLOR;
conf |= ((num_components - 1) <<
TLB_VEC_SIZE_MINUS_1_SHIFT);
b = color[0];
}
+ if (c->fs_key->sample_alpha_to_one)
+ a = vir_uniform_f(c, 1.0);
+
if (c->fs_key->f32_color_rb & (1 << rt)) {
- inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
+ inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
inst->src[vir_get_implicit_uniform_src(inst)] =
vir_uniform_ui(c, conf);
- for (int i = 1; i < num_components; i++) {
- inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
- color[i]);
- }
+ if (num_components >= 2)
+ vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
+ if (num_components >= 3)
+ vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
+ if (num_components >= 4)
+ vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
} else {
inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
if (conf != ~0) {
v3d33_vir_vpm_write_setup(c);
}
+/**
+ * Sets up c->outputs[c->output_position_index] for the vertex shader
+ * epilogue, if an output vertex position wasn't specified in the user's
+ * shader. This may be the case for transform feedback with rasterizer
+ * discard enabled.
+ */
+static void
+setup_default_position(struct v3d_compile *c)
+{
+ if (c->output_position_index != -1)
+ return;
+
+ c->output_position_index = c->outputs_array_size;
+ for (int i = 0; i < 4; i++) {
+ add_output(c,
+ c->output_position_index + i,
+ VARYING_SLOT_POS, i);
+ }
+}
+
static void
emit_vert_end(struct v3d_compile *c)
{
+ setup_default_position(c);
+
uint32_t vpm_index = 0;
struct qreg rcp_w = vir_SFU(c, V3D_QPU_WADDR_RECIP,
c->outputs[c->output_position_index + 3]);
/* GFXH-1684: VPM writes need to be complete by the end of the shader.
*/
- if (c->devinfo->ver >= 40 && c->devinfo->ver <= 41)
+ if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
vir_VPMWT(c);
}
NIR_PASS(progress, s, nir_opt_constant_folding);
NIR_PASS(progress, s, nir_opt_undef);
} while (progress);
+
+ NIR_PASS(progress, s, nir_opt_move_load_ubo);
}
static int
assert(array_len == 1);
(void)array_len;
- for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
+ for (int i = 0; i < 4; i++) {
add_output(c, loc + var->data.location_frac + i,
var->data.location,
var->data.location_frac + i);
static void
ntq_activate_execute_for_block(struct v3d_compile *c)
{
- vir_PF(c, vir_SUB(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
+ vir_PF(c, vir_XOR(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
V3D_QPU_PF_PUSHZ);
vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
vir_uniform_ui(c, after_block->index));
/* If everything points at ENDIF, then jump there immediately. */
- vir_PF(c, vir_SUB(c, c->execute,
+ vir_PF(c, vir_XOR(c, c->execute,
vir_uniform_ui(c, after_block->index)),
V3D_QPU_PF_PUSHZ);
vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
*
* XXX: Use the .ORZ flags update, instead.
*/
- vir_PF(c, vir_SUB(c,
+ vir_PF(c, vir_XOR(c,
c->execute,
vir_uniform_ui(c, c->loop_cont_block->index)),
V3D_QPU_PF_PUSHZ);
vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
- vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
+ struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
+ /* Pixels that were not dispatched or have been discarded should not
+ * contribute to looping again.
+ */
+ branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
vir_link_blocks(c->cur_block, c->loop_cont_block);
vir_link_blocks(c->cur_block, c->loop_break_block);
}
const nir_shader_compiler_options v3d_nir_options = {
+ .lower_all_io_to_temps = true,
.lower_extract_byte = true,
.lower_extract_word = true,
- .lower_bitfield_insert = true,
- .lower_bitfield_extract = true,
+ .lower_bfm = true,
+ .lower_bitfield_insert_to_shifts = true,
+ .lower_bitfield_extract_to_shifts = true,
+ .lower_bitfield_reverse = true,
+ .lower_bit_count = true,
.lower_pack_unorm_2x16 = true,
.lower_pack_snorm_2x16 = true,
.lower_pack_unorm_4x8 = true,
.lower_unpack_unorm_4x8 = true,
.lower_unpack_snorm_4x8 = true,
.lower_fdiv = true,
+ .lower_find_lsb = true,
.lower_ffma = true,
.lower_flrp32 = true,
.lower_fpow = true,
.lower_fsat = true,
.lower_fsqrt = true,
+ .lower_ifind_msb = true,
+ .lower_ldexp = true,
+ .lower_mul_high = true,
.native_integers = true,
};
c->last_thrsw = NULL;
}
-static void
+void
vir_emit_last_thrsw(struct v3d_compile *c)
{
/* On V3D before 4.1, we need a TMU op to be outstanding when thread
c->last_thrsw->is_last_thrsw = true;
}
+/* There's a flag in the shader for "center W is needed for reasons other than
+ * non-centroid varyings", so we just walk the program after VIR optimization
+ * to see if it's used. It should be harmless to set even if we only use
+ * center W for varyings.
+ */
+static void
+vir_check_payload_w(struct v3d_compile *c)
+{
+ if (c->s->info.stage != MESA_SHADER_FRAGMENT)
+ return;
+
+ vir_for_each_inst_inorder(inst, c) {
+ for (int i = 0; i < vir_get_nsrc(inst); i++) {
+ if (inst->src[i].file == QFILE_REG &&
+ inst->src[i].index == 0) {
+ c->uses_center_w = true;
+ return;
+ }
+ }
+ }
+
+}
+
void
v3d_nir_to_vir(struct v3d_compile *c)
{
vir_optimize(c);
vir_lower_uniforms(c);
+ vir_check_payload_w(c);
+
/* XXX: vir_schedule_instructions(c); */
if (V3D_DEBUG & (V3D_DEBUG_VIR |
fprintf(stderr, "\n");
}
- /* Compute the live ranges so we can figure out interference. */
- vir_calculate_live_intervals(c);
-
/* Attempt to allocate registers for the temporaries. If we fail,
* reduce thread count and try again.
*/
int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
struct qpu_reg *temp_registers;
while (true) {
- temp_registers = v3d_register_allocate(c);
+ bool spilled;
+ temp_registers = v3d_register_allocate(c, &spilled);
+ if (spilled)
+ continue;
if (temp_registers)
break;
projects / mesa.git / blobdiff