#include "util/macros.h"
#include "common/v3d_debug.h"
#include "common/v3d_device_info.h"
+#include "common/v3d_limits.h"
#include "compiler/nir/nir.h"
#include "util/list.h"
#include "util/u_math.h"
#include "qpu/qpu_instr.h"
#include "pipe/p_state.h"
-#define V3D_MAX_TEXTURE_SAMPLERS 32
-#define V3D_MAX_SAMPLES 4
-#define V3D_MAX_FS_INPUTS 64
-#define V3D_MAX_VS_INPUTS 64
-
struct nir_builder;
struct v3d_fs_inputs {
return (struct qreg){file, index};
}
+static inline struct qreg vir_nop_reg(void)
+{
+ return (struct qreg){QFILE_NULL, 0};
+}
+
/**
* A reference to an actual register at the QPU level, for register
* allocation.
*/
struct qpu_reg {
bool magic;
+ bool smimm;
int index;
};
*/
QUNIFORM_TEXTURE_CONFIG_P1,
- /* A a V3D 4.x texture config parameter. The high 8 bits will be
+ /* A V3D 4.x texture config parameter. The high 8 bits will be
* which texture or sampler is being sampled, and the driver must
* replace the address field with the appropriate address.
*/
QUNIFORM_TMU_CONFIG_P0,
QUNIFORM_TMU_CONFIG_P1,
+ QUNIFORM_IMAGE_TMU_CONFIG_P0,
+
QUNIFORM_TEXTURE_FIRST_LEVEL,
QUNIFORM_TEXTURE_WIDTH,
QUNIFORM_TEXRECT_SCALE_X,
QUNIFORM_TEXRECT_SCALE_Y,
- QUNIFORM_TEXTURE_BORDER_COLOR,
+ /* Returns the base offset of the SSBO given by the data value. */
+ QUNIFORM_SSBO_OFFSET,
+
+ /* Returns the size of the SSBO given by the data value. */
+ QUNIFORM_GET_BUFFER_SIZE,
- QUNIFORM_STENCIL,
+ /* Sizes (in pixels) of a shader image given by the data value. */
+ QUNIFORM_IMAGE_WIDTH,
+ QUNIFORM_IMAGE_HEIGHT,
+ QUNIFORM_IMAGE_DEPTH,
+ QUNIFORM_IMAGE_ARRAY_SIZE,
QUNIFORM_ALPHA_REF,
- QUNIFORM_SAMPLE_MASK,
+
+ /* Number of workgroups passed to glDispatchCompute in the dimension
+ * selected by the data value.
+ */
+ QUNIFORM_NUM_WORK_GROUPS,
/**
* Returns the the offset of the scratch buffer for register spilling.
*/
QUNIFORM_SPILL_OFFSET,
QUNIFORM_SPILL_SIZE_PER_THREAD,
+
+ /**
+ * Returns the offset of the shared memory for compute shaders.
+ *
+ * This will be accessed using TMU general memory operations, so the
+ * L2T cache will effectively be the shared memory area.
+ */
+ QUNIFORM_SHARED_OFFSET,
};
+static inline uint32_t v3d_tmu_config_data_create(uint32_t unit, uint32_t value)
+{
+ return unit << 24 | value;
+}
+
+static inline uint32_t v3d_tmu_config_data_get_unit(uint32_t data)
+{
+ return data >> 24;
+}
+
+static inline uint32_t v3d_tmu_config_data_get_value(uint32_t data)
+{
+ return data & 0xffffff;
+}
+
struct v3d_varying_slot {
uint8_t slot_and_component;
};
uint8_t swizzle[4];
uint8_t return_size;
uint8_t return_channels;
- unsigned compare_mode:1;
- unsigned compare_func:3;
bool clamp_s:1;
bool clamp_t:1;
bool clamp_r:1;
bool sample_alpha_to_one;
bool clamp_color;
bool shade_model_flat;
- uint8_t nr_cbufs;
+ /* Mask of which color render targets are present. */
+ uint8_t cbufs;
uint8_t swap_color_rb;
/* Mask of which render targets need to be written as 32-bit floats */
uint8_t f32_color_rb;
struct exec_list *cf_node_list;
const struct v3d_compiler *compiler;
+ void (*debug_output)(const char *msg,
+ void *debug_output_data);
+ void *debug_output_data;
+
/**
* Mapping from nir_register * or nir_ssa_def * to array of struct
* qreg for the values.
*/
uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
+ uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
+
uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
- bool uses_centroid_and_center_w;
+ bool uses_center_w;
+ bool writes_z;
struct v3d_ubo_range *ubo_ranges;
bool *ubo_range_used;
/* Fragment shader payload regs. */
struct qreg payload_w, payload_w_centroid, payload_z;
- uint8_t vattr_sizes[V3D_MAX_VS_INPUTS];
+ struct qreg cs_payload[2];
+ struct qreg cs_shared_offset;
+ int local_invocation_index_bits;
+
+ uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
uint32_t num_vpm_writes;
/* Size in bytes of registers that have been spilled. This is how much
* space needs to be available in the spill BO per thread per QPU.
*/
uint32_t spill_size;
- /* Shader-db stats for register spilling. */
- uint32_t spills, fills;
+ /* Shader-db stats */
+ uint32_t spills, fills, loops;
/**
* Register spilling's per-thread base address, shared between each
* spill/fill's addressing calculations.
bool uses_iid, uses_vid;
/* Number of components read from each vertex attribute. */
- uint8_t vattr_sizes[32];
+ uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
/* Total number of components read, for the shader state record. */
uint32_t vpm_input_size;
/* Total number of components written, for the shader state record. */
uint32_t vpm_output_size;
+
+ /* Set if there should be separate VPM segments for input and output.
+ * If unset, vpm_input_size will be 0.
+ */
+ bool separate_segments;
+
+ /* Value to be programmed in VCM_CACHE_SIZE. */
+ uint8_t vcm_cache_size;
};
struct v3d_fs_prog_data {
*/
uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
+ uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
+
uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
bool writes_z;
- bool discard;
- bool uses_centroid_and_center_w;
+ bool disable_ez;
+ bool uses_center_w;
};
/* Special nir_load_input intrinsic index for loading the current TLB
void v3d_compiler_free(const struct v3d_compiler *compiler);
void v3d_optimize_nir(struct nir_shader *s);
-uint64_t *v3d_compile_vs(const struct v3d_compiler *compiler,
- struct v3d_vs_key *key,
- struct v3d_vs_prog_data *prog_data,
- nir_shader *s,
- int program_id, int variant_id,
- uint32_t *final_assembly_size);
-
-uint64_t *v3d_compile_fs(const struct v3d_compiler *compiler,
- struct v3d_fs_key *key,
- struct v3d_fs_prog_data *prog_data,
- nir_shader *s,
- int program_id, int variant_id,
- uint32_t *final_assembly_size);
+uint64_t *v3d_compile(const struct v3d_compiler *compiler,
+ struct v3d_key *key,
+ struct v3d_prog_data **prog_data,
+ nir_shader *s,
+ void (*debug_output)(const char *msg,
+ void *debug_output_data),
+ void *debug_output_data,
+ int program_id, int variant_id,
+ uint32_t *final_assembly_size);
void v3d_nir_to_vir(struct v3d_compile *c);
struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
+void vir_set_uf(struct qinst *inst, enum v3d_qpu_uf uf);
void vir_set_unpack(struct qinst *inst, int src,
enum v3d_qpu_input_unpack unpack);
bool vir_is_tex(struct qinst *inst);
bool vir_is_add(struct qinst *inst);
bool vir_is_mul(struct qinst *inst);
-bool vir_is_float_input(struct qinst *inst);
-bool vir_depends_on_flags(struct qinst *inst);
bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
void vir_dump(struct v3d_compile *c);
void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
+void vir_dump_uniform(enum quniform_contents contents, uint32_t data);
void vir_validate(struct v3d_compile *c);
void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
+void v3d_nir_lower_image_load_store(nir_shader *s);
void vir_lower_uniforms(struct v3d_compile *c);
void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
+void v3d40_vir_emit_image_load_store(struct v3d_compile *c,
+ nir_intrinsic_instr *instr);
void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
struct qpu_reg *v3d_register_allocate(struct v3d_compile *c, bool *spilled);
bool vir_init_reg_sets(struct v3d_compiler *compiler);
-void vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf);
+bool v3d_gl_format_is_return_32(GLenum format);
static inline bool
quniform_contents_is_texture_p0(enum quniform_contents contents)
a, b)); \
}
+#define VIR_SFU(name) \
+static inline struct qreg \
+vir_##name(struct v3d_compile *c, struct qreg a) \
+{ \
+ if (c->devinfo->ver >= 41) { \
+ return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
+ c->undef, \
+ a, c->undef)); \
+ } else { \
+ vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
+ return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
+ } \
+} \
+static inline struct qinst * \
+vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
+ struct qreg a) \
+{ \
+ if (c->devinfo->ver >= 41) { \
+ return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
+ dest, \
+ a, c->undef)); \
+ } else { \
+ vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
+ return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
+ } \
+}
+
#define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
#define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
#define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
VIR_A_ALU2(XOR)
VIR_A_ALU2(VADD)
VIR_A_ALU2(VSUB)
-VIR_A_ALU2(STVPMV)
+VIR_A_NODST_2(STVPMV)
VIR_A_ALU1(NOT)
VIR_A_ALU1(NEG)
VIR_A_ALU1(FLAPUSH)
VIR_A_ALU1(FLBPUSH)
-VIR_A_ALU1(FLBPOP)
+VIR_A_ALU1(FLPOP)
VIR_A_ALU1(SETMSF)
VIR_A_ALU1(SETREVF)
VIR_A_ALU0(TIDX)
VIR_A_ALU0(EIDX)
VIR_A_ALU1(LDVPMV_IN)
VIR_A_ALU1(LDVPMV_OUT)
+VIR_A_ALU0(TMUWT)
VIR_A_ALU0(FXCD)
VIR_A_ALU0(XCD)
VIR_A_ALU0(YCD)
VIR_A_ALU0(MSF)
VIR_A_ALU0(REVF)
+VIR_A_ALU0(BARRIERID)
VIR_A_NODST_1(VPMSETUP)
VIR_A_NODST_0(VPMWT)
VIR_A_ALU2(FCMP)
VIR_M_ALU1(MOV)
VIR_M_ALU1(FMOV)
+VIR_SFU(RECIP)
+VIR_SFU(RSQRT)
+VIR_SFU(EXP)
+VIR_SFU(LOG)
+VIR_SFU(SIN)
+VIR_SFU(RSQRT2)
+
static inline struct qinst *
vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
struct qreg dest, struct qreg src)
*/
static inline struct qinst *
-vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_cond cond)
+vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
{
/* The actual uniform_data value will be set at scheduling time */
return vir_emit_nondef(c, vir_branch_inst(cond, vir_uniform_ui(c, 0)));
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