intel/blorp: Support the RGB workaround on more formats

[mesa.git] / src / broadcom / qpu / qpu_instr.h

diff --git a/src/broadcom/qpu/qpu_instr.h b/src/broadcom/qpu/qpu_instr.h
index cab1885acc4e8e4e437302bf00a0973050c2d682..e5e9a9a3f1f68d1f86f672b949e38ec9bebf1165 100644 (file)
--- a/src/broadcom/qpu/qpu_instr.h
+++ b/src/broadcom/qpu/qpu_instr.h
@@ -107,13 +107,29 @@ enum v3d_qpu_waddr {
         V3D_QPU_WADDR_VPMU = 15,
         V3D_QPU_WADDR_SYNC = 16,
         V3D_QPU_WADDR_SYNCU = 17,
-        /* reserved */
+        V3D_QPU_WADDR_SYNCB = 18,
         V3D_QPU_WADDR_RECIP = 19,
         V3D_QPU_WADDR_RSQRT = 20,
         V3D_QPU_WADDR_EXP = 21,
         V3D_QPU_WADDR_LOG = 22,
         V3D_QPU_WADDR_SIN = 23,
         V3D_QPU_WADDR_RSQRT2 = 24,
+        V3D_QPU_WADDR_TMUC = 32,
+        V3D_QPU_WADDR_TMUS = 33,
+        V3D_QPU_WADDR_TMUT = 34,
+        V3D_QPU_WADDR_TMUR = 35,
+        V3D_QPU_WADDR_TMUI = 36,
+        V3D_QPU_WADDR_TMUB = 37,
+        V3D_QPU_WADDR_TMUDREF = 38,
+        V3D_QPU_WADDR_TMUOFF = 39,
+        V3D_QPU_WADDR_TMUSCM = 40,
+        V3D_QPU_WADDR_TMUSF = 41,
+        V3D_QPU_WADDR_TMUSLOD = 42,
+        V3D_QPU_WADDR_TMUHS = 43,
+        V3D_QPU_WADDR_TMUHSCM = 44,
+        V3D_QPU_WADDR_TMUHSF = 45,
+        V3D_QPU_WADDR_TMUHSLOD = 46,
+        V3D_QPU_WADDR_R5REP = 55,
 };
 
 struct v3d_qpu_flags {
@@ -169,14 +185,17 @@ enum v3d_qpu_add_op {
         V3D_QPU_A_VDWWT,
         V3D_QPU_A_IID,
         V3D_QPU_A_SAMPID,
-        V3D_QPU_A_PATCHID,
+        V3D_QPU_A_BARRIERID,
         V3D_QPU_A_TMUWT,
         V3D_QPU_A_VPMSETUP,
         V3D_QPU_A_VPMWT,
-        V3D_QPU_A_LDVPMV,
-        V3D_QPU_A_LDVPMD,
+        V3D_QPU_A_LDVPMV_IN,
+        V3D_QPU_A_LDVPMV_OUT,
+        V3D_QPU_A_LDVPMD_IN,
+        V3D_QPU_A_LDVPMD_OUT,
         V3D_QPU_A_LDVPMP,
-        V3D_QPU_A_LDVPMG,
+        V3D_QPU_A_LDVPMG_IN,
+        V3D_QPU_A_LDVPMG_OUT,
         V3D_QPU_A_FCMP,
         V3D_QPU_A_VFMAX,
         V3D_QPU_A_FROUND,
@@ -394,6 +413,16 @@ v3d_qpu_flags_unpack(const struct v3d_device_info *devinfo,
                      uint32_t packed_cond,
                      struct v3d_qpu_flags *cond);
 
+bool
+v3d_qpu_small_imm_pack(const struct v3d_device_info *devinfo,
+                       uint32_t value,
+                       uint32_t *packed_small_immediate);
+
+bool
+v3d_qpu_small_imm_unpack(const struct v3d_device_info *devinfo,
+                         uint32_t packed_small_immediate,
+                         uint32_t *small_immediate);
+
 bool
 v3d_qpu_instr_pack(const struct v3d_device_info *devinfo,
                    const struct v3d_qpu_instr *instr,
@@ -408,6 +437,8 @@ bool v3d_qpu_magic_waddr_is_tmu(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
 bool v3d_qpu_magic_waddr_is_tlb(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
 bool v3d_qpu_magic_waddr_is_vpm(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
 bool v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST;
+bool v3d_qpu_uses_tlb(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
+bool v3d_qpu_writes_tmu(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
 bool v3d_qpu_writes_r3(const struct v3d_device_info *devinfo,
                        const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
 bool v3d_qpu_writes_r4(const struct v3d_device_info *devinfo,
@@ -415,6 +446,9 @@ bool v3d_qpu_writes_r4(const struct v3d_device_info *devinfo,
 bool v3d_qpu_writes_r5(const struct v3d_device_info *devinfo,
                        const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST;
 bool v3d_qpu_uses_mux(const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux);
+bool v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
+bool v3d_qpu_reads_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
+bool v3d_qpu_writes_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST;
 bool v3d_qpu_sig_writes_address(const struct v3d_device_info *devinfo,
                                 const struct v3d_qpu_sig *sig) ATTRIBUTE_CONST;