#define VC5_QPU_SIG_SHIFT 53
#define VC5_QPU_SIG_MASK QPU_MASK(57, 53)
-# define VC5_QPU_SIG_THRSW_BIT 0x1
-# define VC5_QPU_SIG_LDUNIF_BIT 0x2
-# define VC5_QPU_SIG_LDTMU_BIT 0x4
-# define VC5_QPU_SIG_LDVARY_BIT 0x8
#define VC5_QPU_COND_SHIFT 46
#define VC5_QPU_COND_MASK QPU_MASK(52, 46)
return false;
}
+static inline unsigned
+fui( float f )
+{
+ union {float f; unsigned ui;} fi;
+ fi.f = f;
+ return fi.ui;
+}
+
+static const uint32_t small_immediates[] = {
+ 0, 1, 2, 3,
+ 4, 5, 6, 7,
+ 8, 9, 10, 11,
+ 12, 13, 14, 15,
+ -16, -15, -14, -13,
+ -12, -11, -10, -9,
+ -8, -7, -6, -5,
+ -4, -3, -2, -1,
+ 0x3b800000, /* 2.0^-8 */
+ 0x3c000000, /* 2.0^-7 */
+ 0x3c800000, /* 2.0^-6 */
+ 0x3d000000, /* 2.0^-5 */
+ 0x3d800000, /* 2.0^-4 */
+ 0x3e000000, /* 2.0^-3 */
+ 0x3e800000, /* 2.0^-2 */
+ 0x3f000000, /* 2.0^-1 */
+ 0x3f800000, /* 2.0^0 */
+ 0x40000000, /* 2.0^1 */
+ 0x40800000, /* 2.0^2 */
+ 0x41000000, /* 2.0^3 */
+ 0x41800000, /* 2.0^4 */
+ 0x42000000, /* 2.0^5 */
+ 0x42800000, /* 2.0^6 */
+ 0x43000000, /* 2.0^7 */
+};
+
+bool
+v3d_qpu_small_imm_unpack(const struct v3d_device_info *devinfo,
+ uint32_t packed_small_immediate,
+ uint32_t *small_immediate)
+{
+ if (packed_small_immediate >= ARRAY_SIZE(small_immediates))
+ return false;
+
+ *small_immediate = small_immediates[packed_small_immediate];
+ return true;
+}
+
+bool
+v3d_qpu_small_imm_pack(const struct v3d_device_info *devinfo,
+ uint32_t value,
+ uint32_t *packed_small_immediate)
+{
+ STATIC_ASSERT(ARRAY_SIZE(small_immediates) == 48);
+
+ for (int i = 0; i < ARRAY_SIZE(small_immediates); i++) {
+ if (small_immediates[i] == value) {
+ *packed_small_immediate = i;
+ return true;
+ }
+ }
+
+ return false;
+}
bool
v3d_qpu_flags_unpack(const struct v3d_device_info *devinfo,
{ 186, 186, 1 << 1, ANYMUX, V3D_QPU_A_NEG },
{ 186, 186, 1 << 2, ANYMUX, V3D_QPU_A_FLAPUSH },
{ 186, 186, 1 << 3, ANYMUX, V3D_QPU_A_FLBPUSH },
- { 186, 186, 1 << 4, ANYMUX, V3D_QPU_A_FLBPOP },
+ { 186, 186, 1 << 4, ANYMUX, V3D_QPU_A_FLPOP },
+ { 186, 186, 1 << 5, ANYMUX, V3D_QPU_A_RECIP },
{ 186, 186, 1 << 6, ANYMUX, V3D_QPU_A_SETMSF },
{ 186, 186, 1 << 7, ANYMUX, V3D_QPU_A_SETREVF },
{ 187, 187, 1 << 0, 1 << 0, V3D_QPU_A_NOP, 0 },
{ 187, 187, 1 << 2, 1 << 0, V3D_QPU_A_MSF },
{ 187, 187, 1 << 2, 1 << 1, V3D_QPU_A_REVF },
- { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_VDWWT },
+ { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_VDWWT, 33 },
+ { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_IID, 40 },
+ { 187, 187, 1 << 2, 1 << 3, V3D_QPU_A_SAMPID, 40 },
+ { 187, 187, 1 << 2, 1 << 4, V3D_QPU_A_BARRIERID, 40 },
{ 187, 187, 1 << 2, 1 << 5, V3D_QPU_A_TMUWT },
{ 187, 187, 1 << 2, 1 << 6, V3D_QPU_A_VPMWT },
- { 187, 187, 1 << 3, ANYMUX, V3D_QPU_A_VPMSETUP },
+ { 187, 187, 1 << 3, ANYMUX, V3D_QPU_A_VPMSETUP, 33 },
+ { 188, 188, 1 << 0, ANYMUX, V3D_QPU_A_LDVPMV_IN, 40 },
+ { 188, 188, 1 << 1, ANYMUX, V3D_QPU_A_LDVPMD_IN, 40 },
+ { 188, 188, 1 << 2, ANYMUX, V3D_QPU_A_LDVPMP, 40 },
+ { 188, 188, 1 << 3, ANYMUX, V3D_QPU_A_RSQRT, 41 },
+ { 188, 188, 1 << 4, ANYMUX, V3D_QPU_A_EXP, 41 },
+ { 188, 188, 1 << 5, ANYMUX, V3D_QPU_A_LOG, 41 },
+ { 188, 188, 1 << 6, ANYMUX, V3D_QPU_A_SIN, 41 },
+ { 188, 188, 1 << 7, ANYMUX, V3D_QPU_A_RSQRT2, 41 },
+ { 189, 189, ANYMUX, ANYMUX, V3D_QPU_A_LDVPMG_IN, 40 },
/* FIXME: MORE COMPLICATED */
/* { 190, 191, ANYMUX, ANYMUX, V3D_QPU_A_VFMOVABSNEGNAB }, */
instr->alu.add.a = mux_a;
instr->alu.add.b = mux_b;
instr->alu.add.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A);
- instr->alu.add.magic_write = packed_inst & VC5_QPU_MA;
+
+ instr->alu.add.magic_write = false;
+ if (packed_inst & VC5_QPU_MA) {
+ switch (instr->alu.add.op) {
+ case V3D_QPU_A_LDVPMV_IN:
+ instr->alu.add.op = V3D_QPU_A_LDVPMV_OUT;
+ break;
+ case V3D_QPU_A_LDVPMD_IN:
+ instr->alu.add.op = V3D_QPU_A_LDVPMD_OUT;
+ break;
+ case V3D_QPU_A_LDVPMG_IN:
+ instr->alu.add.op = V3D_QPU_A_LDVPMG_OUT;
+ break;
+ default:
+ instr->alu.add.magic_write = true;
+ break;
+ }
+ }
return true;
}
if (nsrc < 1)
mux_a = ffs(desc->mux_a_mask) - 1;
+ bool no_magic_write = false;
+
switch (instr->alu.add.op) {
case V3D_QPU_A_STVPMV:
waddr = 0;
+ no_magic_write = true;
break;
case V3D_QPU_A_STVPMD:
waddr = 1;
+ no_magic_write = true;
break;
case V3D_QPU_A_STVPMP:
waddr = 2;
+ no_magic_write = true;
+ break;
+
+ case V3D_QPU_A_LDVPMV_IN:
+ case V3D_QPU_A_LDVPMD_IN:
+ case V3D_QPU_A_LDVPMP:
+ case V3D_QPU_A_LDVPMG_IN:
+ assert(!instr->alu.add.magic_write);
break;
+
+ case V3D_QPU_A_LDVPMV_OUT:
+ case V3D_QPU_A_LDVPMD_OUT:
+ case V3D_QPU_A_LDVPMG_OUT:
+ assert(!instr->alu.add.magic_write);
+ *packed_instr |= VC5_QPU_MA;
+ break;
+
default:
break;
}
*packed_instr |= QPU_SET_FIELD(mux_b, VC5_QPU_ADD_B);
*packed_instr |= QPU_SET_FIELD(opcode, VC5_QPU_OP_ADD);
*packed_instr |= QPU_SET_FIELD(waddr, V3D_QPU_WADDR_A);
- if (instr->alu.add.magic_write)
+ if (instr->alu.add.magic_write && !no_magic_write)
*packed_instr |= VC5_QPU_MA;
return true;