SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------
*/
-package Soc;
+package socgen;
/*====== Package imports === */
import FIFO::*;
import FIFOF::*;
import Vector::*;
import Connectable::*;
import Clocks::*;
- /*========================== */
-{10}
+
/*=== Project imports === */
+ import ifc_sync:: *;
import ConcatReg::*;
import AXI4_Types::*;
import AXI4_Fabric::*;
import defined_types::*;
import MemoryMap :: *;
import slow_peripherals::*;
+ import fast_memory_map::*;
+ import slow_memory_map::*;
`ifdef DEBUG
`include "defines.bsv"
`endif
`include "instance_defines.bsv"
`include "core_parameters.bsv"
{8}
- /*====== AXI4 slave declarations =======*/
-{3}
- /*====== AXI4 Master declarations =======*/
-{4}
-
`ifdef DMA
import DMA :: *;
`ifdef VME
import vme_master::*;
`endif
- `ifdef FlexBus
- import FlexBus_Types::*;
- `endif
{0}
/*========================= */
interface Ifc_Soc;
- interface SP_ios slow_ios;
+ interface SP_dedicated_ios slow_ios;
+ interface IOCellSide iocell_side;
(*always_ready,always_enabled*)
method Action boot_sequence(Bit#(1) bootseq);
`endif
`ifdef DDR
(*prefix="M_AXI"*) interface
- AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
+ AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
`endif
`ifdef HYPER
(*always_ready,always_enabled*)
{1}
endinterface
-function FastTuple2 #(Bool, Bit#(TLog#(Num_Slaves)))
- fn_addr_to_slave_num (Bit#(`PADDR) addr);
-
- if(addr>=`SDRAMMemBase && addr<=`SDRAMMemEnd)
- return tuple2(True,fromInteger(valueOf(Sdram_slave_num)));
- else if(addr>=`DebugBase && addr<=`DebugEnd)
- return tuple2(True,fromInteger(valueOf(Debug_slave_num)));
- `ifdef SDRAM
- else if(addr>=`SDRAMCfgBase && addr<=`SDRAMCfgEnd )
- return tuple2(True,fromInteger(valueOf(Sdram_cfg_slave_num)));
- `endif
- `ifdef BOOTROM
- else if(addr>=`BootRomBase && addr<=`BootRomEnd)
- return tuple2(True,fromInteger(valueOf(BootRom_slave_num)));
- `endif
- `ifdef DMA
- else if(addr>=`DMABase && addr<=`DMAEnd)
- return tuple2(True,fromInteger(valueOf(Dma_slave_num)));
- `endif
- `ifdef VME
- else if(addr>=`VMEBase && addr<=`VMEEnd)
- return tuple2(True,fromInteger(valueOf(VME_slave_num)));
- `endif
- `ifdef TCMemory
- else if(addr>=`TCMBase && addr<=`TCMEnd)
- return tuple2(True,fromInteger(valueOf(TCM_slave_num)));
- `endif
- else
-{11}
- return tuple2(False,?);
-endfunction
-
+ //============ mkSoc module =================
(*synthesize*)
module mkSoc #(Bit#(`VADDR) reset_vector,
Ifc_vme_top vme <-mkvme_top();
`endif
Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
- core_clock, core_reset, uart_clock,
- uart_reset, clocked_by slow_clock ,
- reset_by slow_reset
+ core_clock, core_reset,
+ uart_clock, uart_reset,
+ clocked_by slow_clock, reset_by slow_reset
`ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
+ // clock sync mkConnections
+{12}
+
// Fabric
- AXI4_Fabric_IFC #(Num_Masters, Num_Slaves,
- `ADDR, `DATA,`USERSPACE)
+ AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
+ `PADDR, `DATA,`USERSPACE)
fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
// Connect traffic generators to fabric
mkConnection (dma.mmu, fabric.v_from_masters
[fromInteger(valueOf(DMA_master_num))]);
`endif
+{13}
// Connect fabric to memory slaves
interface master=fabric.v_to_slaves
[fromInteger(valueOf(Sdram_slave_num))];
`endif
- interface slow_ios=slow_peripherals.slow_ios;
+ interface slow_ios = slow_peripherals.slow_ios;
+ interface iocell_side = slow_peripherals.iocell_side;
+
{6}
endmodule
endpackage