typo

[pinmux.git] / src / bsv / bsv_lib / soc_template.bsv

diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv
index cd34d2474135a1e625055850962af277abbeec41..b1acd9702b1f1ea2f9586bc3767201f153e3e899 100644 (file)
--- a/src/bsv/bsv_lib/soc_template.bsv
+++ b/src/bsv/bsv_lib/soc_template.bsv
@@ -46,7 +46,9 @@ package Soc;
     import defined_types::*;
     import MemoryMap            :: *;
     import slow_peripherals::*;
+`ifdef DEBUG
     `include "defines.bsv"
+`endif
     `include "instance_defines.bsv"
 {8}
     /*====== AXI4 slave declarations =======*/
@@ -55,37 +57,36 @@ package Soc;
 {4}
 
 
-        `ifdef DMA
-            import DMA                          :: *;
-        `endif
-        `ifdef BOOTROM
-            import BootRom                     ::*;
-        `endif
-        `ifdef SDRAM
-            import sdr_top                      :: *;
+    `ifdef DMA
+        import DMA                              :: *;
+    `endif
+    `ifdef BOOTROM
+        import BootRom                 ::*;
+    `endif
+    `ifdef SDRAM
+        import sdr_top                  :: *;
+    `endif
+    `ifdef BRAM
+        import Memory_AXI4     ::*;
+    `endif
+    `ifdef TCMemory
+        import TCM::*;
+    `endif
+    `ifdef Debug
+        import DebugModule::*;
+    `else
+        import core::*;
+    `endif
+    `ifdef  VME
+        import vme_top ::*;
     `endif
-        `ifdef BRAM
-            import Memory_AXI4 ::*;
-        `endif
-        `ifdef TCMemory
-            import TCM::*;
-        `endif
-        `ifdef Debug
-            import jtagdtm::*;
-            import DebugModule::*;
-        `else
-            import core::*;
-        `endif
-`ifdef  VME
-            import vme_top ::*;
-`endif
 
-`ifdef VME
-            import vme_master::*;
-`endif
-`ifdef FlexBus
-            import FlexBus_Types::*;
-`endif
+    `ifdef VME
+        import vme_master::*;
+    `endif
+    `ifdef FlexBus
+        import FlexBus_Types::*;
+    `endif
 {0}
 
     /*========================= */
@@ -93,28 +94,26 @@ package Soc;
         interface SP_ios slow_ios;
         (*always_ready,always_enabled*)
         method Action boot_sequence(Bit#(1) bootseq);
-        
-          `ifdef SDRAM 
+            
+        `ifdef SDRAM 
             (*always_ready*) interface Ifc_sdram_out sdram_out; 
         `endif
-      `ifdef DDR
-        (*prefix="M_AXI"*) interface
-                AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
-      `endif
-        `ifdef HYPER
-            (*always_ready,always_enabled*)    
-           interface Ifc_flash ifc_flash;
+        `ifdef DDR
+            (*prefix="M_AXI"*) interface
+                   AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
         `endif
-    /*=============================================== */
-       `ifdef VME
-                interface Vme_out  proc_ifc;
-            interface Data_bus_inf proc_dbus;
+        `ifdef HYPER
+             (*always_ready,always_enabled*)   
+             interface Ifc_flash ifc_flash;
         `endif
-        `ifdef FlexBus
-            interface FlexBus_Master_IFC flexbus_out;
+        /*=============================================== */
+        `ifdef VME
+             interface Vme_out  proc_ifc;
+             interface Data_bus_inf proc_dbus;
         `endif
 {1}
     endinterface
+
     (*synthesize*)
     module mkSoc #(Bit#(`VADDR) reset_vector,
                  Clock slow_clock, Reset slow_reset, Clock uart_clock, 
@@ -123,7 +122,7 @@ package Soc;
         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 {2}
-      `ifdef Debug 
+        `ifdef Debug 
             Ifc_DebugModule core<-mkDebugModule(reset_vector);
         `else
             Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
@@ -134,7 +133,7 @@ package Soc;
         `ifdef SDRAM
             Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
         `endif
-    `ifdef BRAM
+        `ifdef BRAM
             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <- 
                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
         `endif
@@ -147,23 +146,21 @@ package Soc;
             `ifdef VME
             Ifc_vme_top             vme             <-mkvme_top();
             `endif     
-        `ifdef FlexBus
-            AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
-                            flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
-        `endif
         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
-          core_clock, core_reset, uart_clock, 
-          uart_reset, clocked_by slow_clock , reset_by slow_reset 
-          `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );        
+                          core_clock, core_reset, uart_clock, 
+                          uart_reset, clocked_by slow_clock ,
+                          reset_by slow_reset 
+                          `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );        
 
-    // Fabric
-    AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
-                fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
+        // Fabric
+        AXI4_Fabric_IFC #(Num_Masters, Num_Slaves,
+                          `PADDR, `Reg_width,`USERSPACE)
+                        fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 
-    // Connect traffic generators to fabric
-    mkConnection (core.dmem_master,fabric.v_from_masters
+        // Connect traffic generators to fabric
+        mkConnection (core.dmem_master,fabric.v_from_masters
                               [fromInteger(valueOf(Dmem_master_num))]);
-    mkConnection (core.imem_master,    fabric.v_from_masters 
+        mkConnection (core.imem_master,        fabric.v_from_masters 
                               [fromInteger(valueOf(Imem_master_num))]);
         `ifdef Debug
             mkConnection (core.debug_master, fabric.v_from_masters 
@@ -217,11 +214,9 @@ package Soc;
                               [fromInteger(valueOf(VME_slave_num))],
                               vme.slave_axi_vme);
             `endif
-            `ifdef FlexBus
-                mkConnection (fabric.v_to_slaves
-                              [fromInteger(valueOf(FlexBus_slave_num))],
-                              flexbus.axi_side);
-            `endif
+
+//          pin connections
+{9}
 
             // fabric connections
 {5}
@@ -304,9 +299,6 @@ package Soc;
         `ifdef VME
             interface  proc_ifc = vme.proc_ifc;
             interface   proc_dbus = vme.proc_dbus;
-        `endif 
-        `ifdef FlexBus
-            interface flexbus_out = flexbus.flexbus_side;
         `endif 
          method Action boot_sequence(Bit#(1) bootseq) = 
                             core.boot_sequence(bootseq);