idef = os.path.join(bp, 'instance_defines.bsv')
slow = os.path.join(bp, 'slow_peripherals.bsv')
slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
- soc = os.path.join(bp, 'soc.bsv')
+ slowmf = os.path.join(bp, 'slow_memory_map.bsv')
+ slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
+ fastmf = os.path.join(bp, 'fast_memory_map.bsv')
+ fastmt = os.path.join(cwd, 'fast_tuple2_template.bsv')
+ soc = os.path.join(bp, 'socgen.bsv')
soct = os.path.join(cwd, 'soc_template.bsv')
write_pmp(pmp, p, ifaces, iocells)
write_bvp(bvp, p, ifaces)
write_bus(bus, p, ifaces)
write_instances(idef, p, ifaces)
- write_slow(slow, slowt, p, ifaces, iocells)
- write_soc(soc, soct, p, ifaces, iocells)
+ write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells)
+ write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells)
-def write_slow(slow, slowt, p, ifaces, iocells):
+def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells):
""" write out the slow_peripherals.bsv file.
joins all the peripherals together into one AXI Lite interface
"""
- with open(slowt) as bsv_file:
- slowt = bsv_file.read()
imports = ifaces.slowimport()
ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
regdef = ifaces.axi_reg_def()
numsloirqs = ifaces.mk_sloirqsdef()
ifacedef = ifaces.mk_ext_ifacedef()
ifacedef = ifaces.mk_ext_ifacedef()
+ clockcon = ifaces.mk_slowclk_con()
+
with open(slow, "w") as bsv_file:
+ with open(slowt) as f:
+ slowt = f.read()
bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
fnaddrmap, mkslow, mkcon, mkcellcon,
pincon, inst, mkplic,
numsloirqs, ifacedef,
- inst2))
+ inst2, clockcon))
+
+ with open(slowmf, "w") as bsv_file:
+ with open(slowmt) as f:
+ slowmt = f.read()
+ bsv_file.write(slowmt.format(regdef, slavedecl, fnaddrmap))
-def write_soc(soc, soct, p, ifaces, iocells):
+def write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells):
""" write out the soc.bsv file.
joins all the peripherals together as AXI Masters
"""
ifaces.fastbusmode = True # side-effects... shouldn't really do this
- with open(soct) as bsv_file:
- soct = bsv_file.read()
+
imports = ifaces.slowimport()
ifdecl = ifaces.fastifdecl()
-#ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
- regdef = ifaces.axi_reg_def()
+ regdef = ifaces.axi_fastmem_def()
slavedecl = ifaces.axi_fastslave_idx()
mastdecl = ifaces.axi_master_idx()
- fnaddrmap = ifaces.axi_addr_map()
+ fnaddrmap = ifaces.axi_fastaddr_map()
mkfast = ifaces.mkfast_peripheral()
mkcon = ifaces.mk_fast_connection()
mkcellcon = ifaces.mk_cellconn()
- pincon = ifaces.mk_pincon()
+ pincon = ifaces.mk_fast_pincon()
inst = ifaces.extfastifinstance()
mkplic = ifaces.mk_plic()
numsloirqs = ifaces.mk_sloirqsdef()
ifacedef = ifaces.mk_ext_ifacedef()
dma = ifaces.mk_dma_irq()
num_dmachannels = ifaces.num_dmachannels()
+ clockcon = ifaces.mk_fastclk_con()
+
with open(soc, "w") as bsv_file:
+ with open(soct) as f:
+ soct = f.read()
bsv_file.write(soct.format(imports, ifdecl, mkfast,
slavedecl, mastdecl, mkcon,
inst, dma, num_dmachannels,
- pincon,
+ pincon, regdef, fnaddrmap,
+ clockcon,
))
+ with open(fastmf, "w") as bsv_file:
+ with open(fastmt) as f:
+ fastmt = f.read()
+ bsv_file.write(fastmt.format(regdef, slavedecl, mastdecl, fnaddrmap))
+
def write_bus(bus, p, ifaces):
# package and interface declaration followed by
with open(idef, 'w') as bsv_file:
txt = '''\
`define ADDR {0}
-`define PADDR {0}
+`define PADDR {2}
`define DATA {1}
`define Reg_width {1}
`define USERSPACE 0
`define PERFMONITORS 64
`define DCACHE_WAYS 4
`define DCACHE_TAG_BITS 20 // tag_bits = 52
+
+// CLINT
+ `define ClintBase 'h02000000
+ `define ClintEnd 'h020BFFFF
+
`define PLIC
`define PLICBase 'h0c000000
`define PLICEnd 'h10000000
`define BAUD_RATE 5 //130 //
`endif
'''
- bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))
+ bsv_file.write(txt.format(p.ADDR_WIDTH,
+ p.DATA_WIDTH,
+ p.PADDR_WIDTH))