*/
int index;
+ /**
+ * Descriptor set binding for sampler or UBO.
+ */
+ int descriptor_set;
+
/**
* Initial binding point for a sampler or UBO.
*
#define nir_foreach_variable(var, var_list) \
foreach_list_typed(nir_variable, var, node, var_list)
+#define nir_foreach_variable_safe(var, var_list) \
+ foreach_list_typed_safe(nir_variable, var, node, var_list)
+
static inline bool
nir_variable_is_global(const nir_variable *var)
{
return var->data.mode != nir_var_local && var->data.mode != nir_var_param;
}
+/**
+ * Returns the bits in the inputs_read, outputs_written, or
+ * system_values_read bitfield corresponding to this variable.
+ */
+static inline uint64_t
+nir_variable_get_io_mask(nir_variable *var, gl_shader_stage stage)
+{
+ assert(var->data.mode == nir_var_shader_in ||
+ var->data.mode == nir_var_shader_out ||
+ var->data.mode == nir_var_system_value);
+ assert(var->data.location >= 0);
+
+ const struct glsl_type *var_type = var->type;
+ if (stage == MESA_SHADER_GEOMETRY && var->data.mode == nir_var_shader_in) {
+ /* Most geometry shader inputs are per-vertex arrays */
+ if (var->data.location >= VARYING_SLOT_VAR0)
+ assert(glsl_type_is_array(var_type));
+
+ if (glsl_type_is_array(var_type))
+ var_type = glsl_get_array_element(var_type);
+ }
+
+ bool is_vertex_input = (var->data.mode == nir_var_shader_in &&
+ stage == MESA_SHADER_VERTEX);
+ unsigned slots = glsl_count_attribute_slots(var_type, is_vertex_input);
+ return ((1ull << slots) - 1) << var->data.location;
+}
+
typedef struct nir_register {
struct exec_node node;
*/
NIR_INTRINSIC_UCP_ID = 4,
+ /**
+ * The range of a load operation. This specifies the maximum amount of
+ * data starting at the base offset (if any) that can be accessed.
+ */
+ NIR_INTRINSIC_RANGE = 5,
+
+ /**
+ * The Vulkan descriptor set for vulkan_resource_index intrinsic.
+ */
+ NIR_INTRINSIC_DESC_SET = 6,
+
+ /**
+ * The Vulkan descriptor set binding for vulkan_resource_index intrinsic.
+ */
+ NIR_INTRINSIC_BINDING = 7,
+
NIR_INTRINSIC_NUM_INDEX_FLAGS,
} nir_intrinsic_index_flag;
INTRINSIC_IDX_ACCESSORS(base, BASE, int)
INTRINSIC_IDX_ACCESSORS(stream_id, STREAM_ID, unsigned)
INTRINSIC_IDX_ACCESSORS(ucp_id, UCP_ID, unsigned)
+INTRINSIC_IDX_ACCESSORS(range, RANGE, unsigned)
+INTRINSIC_IDX_ACCESSORS(desc_set, DESC_SET, unsigned)
+INTRINSIC_IDX_ACCESSORS(binding, BINDING, unsigned)
/**
* \group texture information
* are simulated by floats.)
*/
bool native_integers;
+
+ /* Indicates that the driver only has zero-based vertex id */
+ bool vertex_id_zero_based;
} nir_shader_compiler_options;
typedef struct nir_shader_info {
gl_shader_stage stage;
} nir_shader;
+static inline nir_function *
+nir_shader_get_entrypoint(nir_shader *shader)
+{
+ assert(exec_list_length(&shader->functions) == 1);
+ struct exec_node *func_node = exec_list_get_head(&shader->functions);
+ nir_function *func = exec_node_data(nir_function, func_node, node);
+ return func;
+}
+
#define nir_foreach_function(shader, func) \
foreach_list_typed(nir_function, func, node, &(shader)->functions)
};
} nir_cursor;
+static inline nir_block *
+nir_cursor_current_block(nir_cursor cursor)
+{
+ if (cursor.option == nir_cursor_before_instr ||
+ cursor.option == nir_cursor_after_instr) {
+ return cursor.instr->block;
+ } else {
+ return cursor.block;
+ }
+}
+
bool nir_cursors_equal(nir_cursor a, nir_cursor b);
static inline nir_cursor
bool nir_lower_locals_to_regs(nir_shader *shader);
-void nir_lower_outputs_to_temporaries(nir_shader *shader);
+void nir_lower_outputs_to_temporaries(nir_shader *shader,
+ nir_function *entrypoint);
+
+void nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint);
void nir_assign_var_locations(struct exec_list *var_list,
unsigned *size,
void nir_lower_vars_to_ssa(nir_shader *shader);
-bool nir_remove_dead_variables(nir_shader *shader);
+bool nir_remove_dead_variables(nir_shader *shader, nir_variable_mode mode);
void nir_move_vec_src_uses_to_dest(nir_shader *shader);
bool nir_lower_vec_to_movs(nir_shader *shader);