*
* \sa nir_variable_mode
*/
- nir_variable_mode mode:11;
+ unsigned mode:11;
/**
* Is the variable read-only?
unsigned per_view:1;
/**
- * \brief Layout qualifier for gl_FragDepth.
+ * \brief Layout qualifier for gl_FragDepth. See nir_depth_layout.
*
* This is not equal to \c ir_depth_layout_none if and only if this
* variable is \c gl_FragDepth and a layout qualifier is specified.
*/
- nir_depth_layout depth_layout:3;
+ unsigned depth_layout:3;
/**
* Vertex stream output identifier.
unsigned stream:9;
/**
+ * See gl_access_qualifier.
+ *
* Access flags for memory variables (SSBO/global), image uniforms, and
* bindless images in uniforms/inputs/outputs.
*/
- enum gl_access_qualifier access:8;
+ unsigned access:8;
/**
* Descriptor set binding for sampler or UBO.
case nir_op_flt:
case nir_op_fge:
case nir_op_feq:
- case nir_op_fne:
+ case nir_op_fneu:
case nir_op_ilt:
case nir_op_ult:
case nir_op_ige:
const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic]; \
assert(info->index_map[NIR_INTRINSIC_##flag] > 0); \
instr->const_index[info->index_map[NIR_INTRINSIC_##flag] - 1] = val; \
+} \
+static inline bool \
+nir_intrinsic_has_##name(nir_intrinsic_instr *instr) \
+{ \
+ const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic]; \
+ return info->index_map[NIR_INTRINSIC_##flag] > 0; \
}
INTRINSIC_IDX_ACCESSORS(write_mask, WRMASK, unsigned)
* NIR loop is implemented as "while (1) { body }".
*/
nir_jump_continue,
+
+ /** Jumps for unstructured CFG.
+ *
+ * As within an unstructured CFG we can't rely on block ordering we need to
+ * place explicit jumps at the end of every block.
+ */
+ nir_jump_goto,
+ nir_jump_goto_if,
} nir_jump_type;
typedef struct {
nir_instr instr;
nir_jump_type type;
+ nir_src condition;
+ struct nir_block *target;
+ struct nir_block *else_target;
} nir_jump_instr;
/* creates a new SSA variable in an undefined state */
/** lowers fsub and isub to fadd+fneg and iadd+ineg. */
bool lower_sub;
- /* lower {slt,sge,seq,sne} to {flt,fge,feq,fne} + b2f: */
+ /* lower {slt,sge,seq,sne} to {flt,fge,feq,fneu} + b2f: */
bool lower_scmp;
/* lower fall_equalN/fany_nequalN (ex:fany_nequal4 to sne+fdot4+fsat) */
/** enables rules to lower fsign to fsub and flt */
bool lower_fsign;
+ /** enables rules to lower iabs to ineg+imax */
+ bool lower_iabs;
+
/* lower fdph to fdot4 */
bool lower_fdph;
bool lower_pack_snorm_2x16;
bool lower_pack_unorm_4x8;
bool lower_pack_snorm_4x8;
+ bool lower_pack_64_2x32_split;
+ bool lower_pack_32_2x16_split;
bool lower_unpack_half_2x16;
bool lower_unpack_unorm_2x16;
bool lower_unpack_snorm_2x16;
bool lower_unpack_unorm_4x8;
bool lower_unpack_snorm_4x8;
+ bool lower_unpack_64_2x32_split;
+ bool lower_unpack_32_2x16_split;
bool lower_pack_split;
bool lower_cs_local_index_from_id;
bool lower_cs_local_id_from_index;
+ /* Prevents lowering global_invocation_id to be in terms of work_group_id */
+ bool has_cs_global_id;
+
bool lower_device_index_to_zero;
/* Set if nir_lower_wpos_ytransform() should also invert gl_PointCoord. */
*/
nir_address_format_32bit_index_offset,
+ /**
+ * An address format which is a 64-bit value, where the high 32 bits
+ * are a buffer index, and the low 32 bits are an offset.
+ */
+ nir_address_format_32bit_index_offset_pack64,
+
/**
* An address format which is comprised of a vec3 where the first two
* components specify the buffer and the third is an offset.
*/
nir_address_format_32bit_offset,
+ /**
+ * An address format which is a simple 32-bit offset cast to 64-bit.
+ */
+ nir_address_format_32bit_offset_as_64bit,
+
/**
* An address format representing a purely logical addressing model. In
* this model, all deref chains must be complete from the dereference
case nir_address_format_64bit_global: return 64;
case nir_address_format_64bit_bounded_global: return 32;
case nir_address_format_32bit_index_offset: return 32;
+ case nir_address_format_32bit_index_offset_pack64: return 64;
case nir_address_format_vec2_index_32bit_offset: return 32;
case nir_address_format_32bit_offset: return 32;
+ case nir_address_format_32bit_offset_as_64bit: return 64;
case nir_address_format_logical: return 32;
}
unreachable("Invalid address format");
case nir_address_format_64bit_global: return 1;
case nir_address_format_64bit_bounded_global: return 4;
case nir_address_format_32bit_index_offset: return 2;
+ case nir_address_format_32bit_index_offset_pack64: return 1;
case nir_address_format_vec2_index_32bit_offset: return 3;
case nir_address_format_32bit_offset: return 1;
+ case nir_address_format_32bit_offset_as_64bit: return 1;
case nir_address_format_logical: return 1;
}
unreachable("Invalid address format");
bool nir_lower_io_to_vector(nir_shader *shader, nir_variable_mode mask);
bool nir_lower_fragcolor(nir_shader *shader);
-void nir_lower_fragcoord_wtrans(nir_shader *shader);
+bool nir_lower_fragcoord_wtrans(nir_shader *shader);
void nir_lower_viewport_transform(nir_shader *shader);
bool nir_lower_uniforms_to_ubo(nir_shader *shader, int multiplier);
bool nir_lower_system_values(nir_shader *shader);
+typedef struct nir_lower_compute_system_values_options {
+ bool has_base_global_invocation_id:1;
+ bool has_base_work_group_id:1;
+} nir_lower_compute_system_values_options;
+
+bool nir_lower_compute_system_values(nir_shader *shader,
+ const nir_lower_compute_system_values_options *options);
+
enum PACKED nir_lower_tex_packing {
nir_lower_tex_packing_none = 0,
/* The sampler returns up to 2 32-bit words of half floats or 16-bit signed
bool nir_lower_idiv(nir_shader *shader, enum nir_lower_idiv_path path);
-bool nir_lower_input_attachments(nir_shader *shader, bool use_fragcoord_sysval);
+typedef struct nir_input_attachment_options {
+ bool use_fragcoord_sysval;
+ bool use_layer_id_sysval;
+ bool use_view_id_for_layer;
+} nir_input_attachment_options;
+
+bool nir_lower_input_attachments(nir_shader *shader,
+ const nir_input_attachment_options *options);
bool nir_lower_clip_vs(nir_shader *shader, unsigned ucp_enables,
bool use_vars,
bool nir_lower_memory_model(nir_shader *shader);
+bool nir_lower_goto_ifs(nir_shader *shader);
+
bool nir_normalize_cubemap_coords(nir_shader *shader);
void nir_live_ssa_defs_impl(nir_function_impl *impl);
nir_should_vectorize_mem_func callback,
nir_variable_mode robust_modes);
-void nir_strip(nir_shader *shader);
-
void nir_sweep(nir_shader *shader);
void nir_remap_dual_slot_attributes(nir_shader *shader,