i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type

[mesa.git] / src / compiler / nir / nir_builder.h

diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index 2eaa02506561bcf46143db72f1a0a49d0c1fe7b4..7dbf8efbb34115eb9eaeaeb6c50e5d294a7373fc 100644 (file)
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -252,6 +252,17 @@ nir_imm_int(nir_builder *build, int x)
    return nir_build_imm(build, 1, 32, v);
 }
 
+static inline nir_ssa_def *
+nir_imm_int64(nir_builder *build, int64_t x)
+{
+   nir_const_value v;
+
+   memset(&v, 0, sizeof(v));
+   v.i64[0] = x;
+
+   return nir_build_imm(build, 1, 64, v);
+}
+
 static inline nir_ssa_def *
 nir_imm_ivec4(nir_builder *build, int x, int y, int z, int w)
 {
@@ -317,6 +328,10 @@ nir_build_alu(nir_builder *build, nir_op op, nir_ssa_def *src0,
       }
    }
 
+   /* When in doubt, assume 32. */
+   if (bit_size == 0)
+      bit_size = 32;
+
    /* Make sure we don't swizzle from outside of our source vector (like if a
     * scalar value was passed into a multiply with a vector).
     */
@@ -480,7 +495,7 @@ nir_ssa_for_src(nir_builder *build, nir_src src, int num_components)
 }
 
 /**
- * Similar to nir_ssa_for_src(), but for alu src's, respecting the
+ * Similar to nir_ssa_for_src(), but for alu srcs, respecting the
  * nir_alu_src's swizzle.
  */
 static inline nir_ssa_def *