nir: Fix printing of individual instructions with io semantics.

[mesa.git] / src / compiler / nir / nir_opcodes_c.py

diff --git a/src/compiler/nir/nir_opcodes_c.py b/src/compiler/nir/nir_opcodes_c.py
index 8afccca9504f8a73e8f5bac3d751319e9a90908e..c6e5bb39dddff7c07fe7e953014aa1cce398bd13 100644 (file)
--- a/src/compiler/nir/nir_opcodes_c.py
+++ b/src/compiler/nir/nir_opcodes_c.py
@@ -23,7 +23,9 @@
 # Authors:
 #    Connor Abbott (cwabbott0@gmail.com)
 
-from nir_opcodes import opcodes
+from __future__ import print_function
+
+from nir_opcodes import opcodes, type_sizes
 from mako.template import Template
 
 template = Template("""
@@ -38,21 +40,23 @@ nir_type_conversion_op(nir_alu_type src, nir_alu_type dst, nir_rounding_mode rnd
    unsigned dst_bit_size = nir_alu_type_get_type_size(dst);
 
    if (src == dst && src_base == nir_type_float) {
-      return nir_op_fmov;
+      return nir_op_mov;
+   } else if (src == dst && src_base == nir_type_bool) {
+      return nir_op_mov;
    } else if ((src_base == nir_type_int || src_base == nir_type_uint) &&
               (dst_base == nir_type_int || dst_base == nir_type_uint) &&
               src_bit_size == dst_bit_size) {
       /* Integer <-> integer conversions with the same bit-size on both
        * ends are just no-op moves.
        */
-      return nir_op_imov;
+      return nir_op_mov;
    }
 
    switch (src_base) {
-%     for src_t in ['int', 'uint', 'float']:
+%     for src_t in ['int', 'uint', 'float', 'bool']:
       case nir_type_${src_t}:
          switch (dst_base) {
-%           for dst_t in ['int', 'uint', 'float']:
+%           for dst_t in ['int', 'uint', 'float', 'bool']:
             case nir_type_${dst_t}:
 %              if src_t in ['int', 'uint'] and dst_t in ['int', 'uint']:
 %                 if dst_t == 'int':
@@ -60,21 +64,24 @@ nir_type_conversion_op(nir_alu_type src, nir_alu_type dst, nir_rounding_mode rnd
 %                 else:
 <%                   dst_t = src_t %>
 %                 endif
-%              endif
-               switch (dst_bit_size) {
-%                 if dst_t == 'float':
-<%                    bit_sizes = [16, 32, 64] %>
+%              elif src_t == 'bool' and dst_t in ['int', 'uint', 'bool']:
+%                 if dst_t == 'int':
+<%                   continue %>
 %                 else:
-<%                    bit_sizes = [8, 16, 32, 64] %>
+<%                   dst_t = 'int' %>
 %                 endif
-%                 for dst_bits in bit_sizes:
+%              elif src_t == 'uint' and dst_t == 'bool':
+<%                src_t = 'int' %>
+%              endif
+               switch (dst_bit_size) {
+%                 for dst_bits in type_sizes(dst_t):
                   case ${dst_bits}:
 %                    if src_t == 'float' and dst_t == 'float' and dst_bits == 16:
                      switch(rnd) {
-%                       for rnd_t in ['rtne', 'rtz', 'undef']:
-                        case nir_rounding_mode_${rnd_t}:
-                           return ${'nir_op_{0}2{1}{2}_{3}'.format(src_t[0], dst_t[0],
-                                                                   dst_bits, rnd_t)};
+%                       for rnd_t in [('rtne', '_rtne'), ('rtz', '_rtz'), ('undef', '')]:
+                        case nir_rounding_mode_${rnd_t[0]}:
+                           return ${'nir_op_{0}2{1}{2}{3}'.format(src_t[0], dst_t[0],
+                                                                   dst_bits, rnd_t[1])};
 %                       endfor
                         default:
                            unreachable("Invalid 16-bit nir rounding mode");
@@ -88,33 +95,17 @@ nir_type_conversion_op(nir_alu_type src, nir_alu_type dst, nir_rounding_mode rnd
                      unreachable("Invalid nir alu bit size");
                }
 %           endfor
-            case nir_type_bool:
-%              if src_t == 'float':
-                  return nir_op_f2b;
-%              else:
-                  return nir_op_i2b;
-%              endif
             default:
                unreachable("Invalid nir alu base type");
          }
 %     endfor
-      case nir_type_bool:
-         switch (dst_base) {
-            case nir_type_int:
-            case nir_type_uint:
-               return nir_op_b2i;
-            case nir_type_float:
-               return nir_op_b2f;
-            default:
-               unreachable("Invalid nir alu base type");
-         }
       default:
          unreachable("Invalid nir alu base type");
    }
 }
 
 const nir_op_info nir_op_infos[nir_num_opcodes] = {
-% for name, opcode in sorted(opcodes.iteritems()):
+% for name, opcode in sorted(opcodes.items()):
 {
    .name = "${name}",
    .num_inputs = ${opcode.num_inputs},
@@ -126,6 +117,7 @@ const nir_op_info nir_op_infos[nir_num_opcodes] = {
    .input_types = {
       ${ ", ".join("nir_type_" + type for type in opcode.input_types) }
    },
+   .is_conversion = ${"true" if opcode.is_conversion else "false"},
    .algebraic_properties =
       ${ "0" if opcode.algebraic_properties == "" else " | ".join(
             "NIR_OP_IS_" + prop.upper() for prop in
@@ -135,4 +127,4 @@ const nir_op_info nir_op_infos[nir_num_opcodes] = {
 };
 """)
 
-print template.render(opcodes=opcodes)
+print(template.render(opcodes=opcodes, type_sizes=type_sizes))