spirv/amd: Use vtn_push_nir_ssa

[mesa.git] / src / compiler / spirv / vtn_amd.c

diff --git a/src/compiler/spirv/vtn_amd.c b/src/compiler/spirv/vtn_amd.c
index ae7c7af22488af389c11e3e512c1f2e72118ea4c..32420fccae01af090847e7f6c3bac2fda9f0bb30 100644 (file)
--- a/src/compiler/spirv/vtn_amd.c
+++ b/src/compiler/spirv/vtn_amd.c
@@ -30,16 +30,13 @@ bool
 vtn_handle_amd_gcn_shader_instruction(struct vtn_builder *b, SpvOp ext_opcode,
                                       const uint32_t *w, unsigned count)
 {
-   const struct glsl_type *dest_type = vtn_get_type(b, w[1])->type;
-   struct vtn_value *val = vtn_push_value(b, w[2], vtn_value_type_ssa);
-   val->ssa = vtn_create_ssa_value(b, dest_type);
-
+   nir_ssa_def *def;
    switch ((enum GcnShaderAMD)ext_opcode) {
    case CubeFaceIndexAMD:
-      val->ssa->def = nir_cube_face_index(&b->nb, vtn_ssa_value(b, w[5])->def);
-         break;
+      def = nir_cube_face_index(&b->nb, vtn_ssa_value(b, w[5])->def);
+      break;
    case CubeFaceCoordAMD:
-      val->ssa->def = nir_cube_face_coord(&b->nb, vtn_ssa_value(b, w[5])->def);
+      def = nir_cube_face_coord(&b->nb, vtn_ssa_value(b, w[5])->def);
       break;
    case TimeAMD: {
       nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(b->nb.shader,
@@ -47,12 +44,15 @@ vtn_handle_amd_gcn_shader_instruction(struct vtn_builder *b, SpvOp ext_opcode,
       nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, 32, NULL);
       nir_intrinsic_set_memory_scope(intrin, NIR_SCOPE_SUBGROUP);
       nir_builder_instr_insert(&b->nb, &intrin->instr);
-      val->ssa->def = nir_pack_64_2x32(&b->nb, &intrin->dest.ssa);
+      def = nir_pack_64_2x32(&b->nb, &intrin->dest.ssa);
       break;
    }
    default:
       unreachable("Invalid opcode");
    }
+
+   vtn_push_nir_ssa(b, w[2], def);
+
    return true;
 }
 
@@ -60,10 +60,6 @@ bool
 vtn_handle_amd_shader_ballot_instruction(struct vtn_builder *b, SpvOp ext_opcode,
                                          const uint32_t *w, unsigned count)
 {
-   const struct glsl_type *dest_type = vtn_get_type(b, w[1])->type;
-   struct vtn_value *val = vtn_push_value(b, w[2], vtn_value_type_ssa);
-   val->ssa = vtn_create_ssa_value(b, dest_type);
-
    unsigned num_args;
    nir_intrinsic_op op;
    switch ((enum ShaderBallotAMD)ext_opcode) {
@@ -87,6 +83,7 @@ vtn_handle_amd_shader_ballot_instruction(struct vtn_builder *b, SpvOp ext_opcode
       unreachable("Invalid opcode");
    }
 
+   const struct glsl_type *dest_type = vtn_get_type(b, w[1])->type;
    nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(b->nb.shader, op);
    nir_ssa_dest_init_for_type(&intrin->instr, &intrin->dest, dest_type, NULL);
    if (nir_intrinsic_infos[op].src_components[0] == 0)
@@ -112,7 +109,7 @@ vtn_handle_amd_shader_ballot_instruction(struct vtn_builder *b, SpvOp ext_opcode
    }
 
    nir_builder_instr_insert(&b->nb, &intrin->instr);
-   val->ssa->def = &intrin->dest.ssa;
+   vtn_push_nir_ssa(b, w[2], &intrin->dest.ssa);
 
    return true;
 }
@@ -122,9 +119,6 @@ vtn_handle_amd_shader_trinary_minmax_instruction(struct vtn_builder *b, SpvOp ex
                                                  const uint32_t *w, unsigned count)
 {
    struct nir_builder *nb = &b->nb;
-   const struct glsl_type *dest_type = vtn_get_type(b, w[1])->type;
-   struct vtn_value *val = vtn_push_value(b, w[2], vtn_value_type_ssa);
-   val->ssa = vtn_create_ssa_value(b, dest_type);
 
    unsigned num_inputs = count - 5;
    assert(num_inputs == 3);
@@ -132,39 +126,42 @@ vtn_handle_amd_shader_trinary_minmax_instruction(struct vtn_builder *b, SpvOp ex
    for (unsigned i = 0; i < num_inputs; i++)
       src[i] = vtn_ssa_value(b, w[i + 5])->def;
 
+   nir_ssa_def *def;
    switch ((enum ShaderTrinaryMinMaxAMD)ext_opcode) {
    case FMin3AMD:
-      val->ssa->def = nir_fmin3(nb, src[0], src[1], src[2]);
+      def = nir_fmin3(nb, src[0], src[1], src[2]);
       break;
    case UMin3AMD:
-      val->ssa->def = nir_umin3(nb, src[0], src[1], src[2]);
+      def = nir_umin3(nb, src[0], src[1], src[2]);
       break;
    case SMin3AMD:
-      val->ssa->def = nir_imin3(nb, src[0], src[1], src[2]);
+      def = nir_imin3(nb, src[0], src[1], src[2]);
       break;
    case FMax3AMD:
-      val->ssa->def = nir_fmax3(nb, src[0], src[1], src[2]);
+      def = nir_fmax3(nb, src[0], src[1], src[2]);
       break;
    case UMax3AMD:
-      val->ssa->def = nir_umax3(nb, src[0], src[1], src[2]);
+      def = nir_umax3(nb, src[0], src[1], src[2]);
       break;
    case SMax3AMD:
-      val->ssa->def = nir_imax3(nb, src[0], src[1], src[2]);
+      def = nir_imax3(nb, src[0], src[1], src[2]);
       break;
    case FMid3AMD:
-      val->ssa->def = nir_fmed3(nb, src[0], src[1], src[2]);
+      def = nir_fmed3(nb, src[0], src[1], src[2]);
       break;
    case UMid3AMD:
-      val->ssa->def = nir_umed3(nb, src[0], src[1], src[2]);
+      def = nir_umed3(nb, src[0], src[1], src[2]);
       break;
    case SMid3AMD:
-      val->ssa->def = nir_imed3(nb, src[0], src[1], src[2]);
+      def = nir_imed3(nb, src[0], src[1], src[2]);
       break;
    default:
       unreachable("unknown opcode\n");
       break;
    }
 
+   vtn_push_nir_ssa(b, w[2], def);
+
    return true;
 }
 
@@ -172,10 +169,6 @@ bool
 vtn_handle_amd_shader_explicit_vertex_parameter_instruction(struct vtn_builder *b, SpvOp ext_opcode,
                                                             const uint32_t *w, unsigned count)
 {
-   const struct glsl_type *dest_type = vtn_get_type(b, w[1])->type;
-   struct vtn_value *val = vtn_push_value(b, w[2], vtn_value_type_ssa);
-   val->ssa = vtn_create_ssa_value(b, dest_type);
-
    nir_intrinsic_op op;
    switch ((enum ShaderExplicitVertexParameterAMD)ext_opcode) {
    case InterpolateAtVertexAMD:
@@ -214,13 +207,15 @@ vtn_handle_amd_shader_explicit_vertex_parameter_instruction(struct vtn_builder *
 
    nir_builder_instr_insert(&b->nb, &intrin->instr);
 
+   nir_ssa_def *def;
    if (vec_array_deref) {
       assert(vec_deref);
-      val->ssa->def = nir_vector_extract(&b->nb, &intrin->dest.ssa,
-                                         vec_deref->arr.index.ssa);
+      def = nir_vector_extract(&b->nb, &intrin->dest.ssa,
+                               vec_deref->arr.index.ssa);
    } else {
-      val->ssa->def = &intrin->dest.ssa;
+      def = &intrin->dest.ssa;
    }
+   vtn_push_nir_ssa(b, w[2], def);
 
    return true;
 }