compiler: add INTERP_MODE_COLOR for radeonsi

[mesa.git] / src / compiler / spirv / vtn_opencl.c

diff --git a/src/compiler/spirv/vtn_opencl.c b/src/compiler/spirv/vtn_opencl.c
index ba3d00a7ce4ca0ed05ecc908421b5bce614ffbaa..b5e92dc3b85e1d53ccb321747bf8e74ec2201c73 100644 (file)
--- a/src/compiler/spirv/vtn_opencl.c
+++ b/src/compiler/spirv/vtn_opencl.c
@@ -45,7 +45,7 @@ handle_instr(struct vtn_builder *b, enum OpenCLstd_Entrypoints opcode,
    nir_ssa_def *srcs[3] = { NULL };
    vtn_assert(num_srcs <= ARRAY_SIZE(srcs));
    for (unsigned i = 0; i < num_srcs; i++) {
-      srcs[i] = vtn_ssa_value(b, w[i + 5])->def;
+      srcs[i] = vtn_get_nir_ssa(b, w[i + 5]);
    }
 
    nir_ssa_def *result = handler(b, opcode, num_srcs, srcs, dest_type);
@@ -117,8 +117,11 @@ handle_alu(struct vtn_builder *b, enum OpenCLstd_Entrypoints opcode,
            unsigned num_srcs, nir_ssa_def **srcs,
            const struct glsl_type *dest_type)
 {
-   return nir_build_alu(&b->nb, nir_alu_op_for_opencl_opcode(b, opcode),
-                        srcs[0], srcs[1], srcs[2], NULL);
+   nir_ssa_def *ret = nir_build_alu(&b->nb, nir_alu_op_for_opencl_opcode(b, opcode),
+                                    srcs[0], srcs[1], srcs[2], NULL);
+   if (opcode == OpenCLstd_Popcount)
+      ret = nir_u2u(&b->nb, ret, glsl_get_bit_size(dest_type));
+   return ret;
 }
 
 static nir_ssa_def *
@@ -230,7 +233,7 @@ _handle_v_load_store(struct vtn_builder *b, enum OpenCLstd_Entrypoints opcode,
    const struct glsl_type *dest_type = type->type;
    unsigned components = glsl_get_vector_elements(dest_type);
 
-   nir_ssa_def *offset = vtn_ssa_value(b, w[5 + a])->def;
+   nir_ssa_def *offset = vtn_get_nir_ssa(b, w[5 + a]);
    struct vtn_value *p = vtn_value(b, w[6 + a], vtn_value_type_pointer);
 
    struct vtn_ssa_value *comps[NIR_MAX_VEC_COMPONENTS];
@@ -281,6 +284,21 @@ handle_printf(struct vtn_builder *b, enum OpenCLstd_Entrypoints opcode,
    return nir_imm_int(&b->nb, -1);
 }
 
+static nir_ssa_def *
+handle_round(struct vtn_builder *b, enum OpenCLstd_Entrypoints opcode,
+             unsigned num_srcs, nir_ssa_def **srcs,
+             const struct glsl_type *dest_type)
+{
+   nir_ssa_def *src = srcs[0];
+   nir_builder *nb = &b->nb;
+   nir_ssa_def *half = nir_imm_floatN_t(nb, 0.5, src->bit_size);
+   nir_ssa_def *truncated = nir_ftrunc(nb, src);
+   nir_ssa_def *remainder = nir_fsub(nb, src, truncated);
+
+   return nir_bcsel(nb, nir_fge(nb, nir_fabs(nb, remainder), half),
+                    nir_fadd(nb, truncated, nir_fsign(nb, src)), truncated);
+}
+
 static nir_ssa_def *
 handle_shuffle(struct vtn_builder *b, enum OpenCLstd_Entrypoints opcode, unsigned num_srcs,
                nir_ssa_def **srcs, const struct glsl_type *dest_type)
@@ -435,6 +453,9 @@ vtn_handle_opencl_instruction(struct vtn_builder *b, SpvOp ext_opcode,
    case OpenCLstd_Shuffle2:
       handle_instr(b, cl_opcode, w, count, handle_shuffle2);
       return true;
+   case OpenCLstd_Round:
+      handle_instr(b, cl_opcode, w, count, handle_round);
+      return true;
    case OpenCLstd_Printf:
       handle_instr(b, cl_opcode, w, count, handle_printf);
       return true;