Merge with head.

[gem5.git] / src / cpu / BaseCPU.py

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 6c2aace5153aec13ef700d678f71ab43afb9c010..8be84392dd39159f23799251f07f67ae2ee012b5 100644 (file)
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -31,8 +31,12 @@ from m5.params import *
 from m5.proxy import *
 from m5 import build_env
 from Bus import Bus
+from InstTracer import InstTracer
+from ExeTracer import ExeTracer
 import sys
 
+default_tracer = ExeTracer()
+
 if build_env['FULL_SYSTEM']:
     if build_env['TARGET_ISA'] == 'alpha':
         from AlphaTLB import AlphaDTB, AlphaITB
@@ -83,6 +87,8 @@ class BaseCPU(SimObject):
     clock = Param.Clock('1t', "clock speed")
     phase = Param.Latency('0ns', "clock phase")
 
+    tracer = Param.InstTracer(default_tracer, "Instruction tracer")
+
     _mem_ports = []
 
     def connectMemPorts(self, bus):